搜索资源列表
Div
- VHDL新手入门：10分频器的实现 附带波形仿真 -VHDL Getting Started: 10 dividers with waveform simulation implementation
Fenpin
- 基于VHDL语言时钟晶振48Mhz的分频器的制作能够实现1HZ分频的时钟信号。-48Mhz clock oscillator based on VHDL language to achieve the production of crossover frequency of the clock signal 1HZ.
16_fenpinqi
- 这是一个用VHDL语言实现的16位分频器，能够实现分频作用，是一个完整的代码，大家可以参详参详。-This is a VHDL language with 16-bit divider, frequency effects can be achieved, is a complete code, we can participate in detailed reference.
diwu
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
di
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
fenpinqi
- 基于VHDL 语言的分频器设计， EDA； CPLD； VHDL； 仿真-Divider based on VHDL language design, EDA CPLD VHDL Simulation
61EDA_D807
- VHDL数频分频器设计 整数，奇数，偶数，半数等的分频 -VHDL design of an integer number of frequency divider, odd, even, half of the frequency, etc.
fenpin-FPGA
- 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from
dvf
- 基于VHDL语言关于分频器进行基本设计，简单易懂-Divider based on VHDL, the basic design, easy to understand
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
001
- vhdl 语言 用计数器实现分频 N分频器的设计-frequency counter vhdl language
vhdl2
- VHDL语言程序 用于偶数分频器 偶数值可修改-VHDL language program for the even-divider values can be modified even
fpq
- 基于VHDL硬件描述语言的分频器的仿真实例与操作步骤-VHDL hardware descr iption language based on the divider of the simulation and the steps
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
clk_div2
- 本源码是分频器的VHDL,在QUARTUS2下已进行仿真和验证，-The source is the divider of the VHDL, have been carried out under the QUARTUS2 simulation and verification,
VHDL_divider
- 基于VHDL的数控分频器设计及应用.基于VHDL的数控分频器设计，整个过程简单、快捷、可移植性强-VHDL-based design and application of NC divider
deccount2.5
- 2.5分频器设计,用VHDL编写-2.5 divider design using VHDL
09081113
- 简单计数器，分频器，全加器等vhdl程序等-Simple counter, divider, adder vhdl procedures such as
fp15
- 这是一个利用VHDL编写的15分频器，只要在源程序中适当改变参数就可以实现你所要的任意分频。-It is written in a 15 divider using VHDL, as long as the appropriate change in the source parameters can be achieved at any point you want to frequent.