搜索资源列表
altera_fifo
- altera 公司的 FIFO 文档,这是设计同步或异步FIFO的重要文档-altera s FIFO document
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
asyn_fifo
- verilog编写的异步fifo源代码,asyn_fifo.v为顶层,调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计,供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
75448172geleicounter
- 这是异步fifo的vhdl实现代码,已经在FPGA上通过实践证明,运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
asynFifo
- 异步fifo在IC设计中,非常重要;是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙,精简。 -vhdl fifo sound code
asynfifo
- 异步fifo,用Verilog编写,包含testbench,已经通过调试,需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
fifo
- 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
FIFO
- 异步fifo,希望能给大家带来帮助-异步fifo
Asynchronous_FIFO_v6_1
- 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用,介绍如下: Chapter3:schematic和vhdl文件夹,分别是数字钟设计的原理图文件和VHDL程序; Chapter4:multiplier文件夹,串并乘法器设计程序(提示:先编译程序包); Chapter5:sci文件夹,串行通信接口设计程序; Chapter6:watchdog文件夹,看门狗设计程序; Chapter7:taxi文件夹,出租车计价器设计程序; Chapte
fifo_design
- 异步fifo的设计,能够很好的的完成,数据的缓冲,内部有ram存储器-The design of asynchronous fifo, Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
async_fifo
- 异步fifo 源程序代码 欢迎大家学习 用VHDL语言编写-asy fifo
afifo_0916
- 异步FIFO,使用XILINX产品实现,可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
fifo
- 很多关于FIFO的文章其实讨论的都是空/满标志的不同算法问题。 在Vijay A. Nebhrajani的《异步FIFO结构》一文中,作者提出了两个关于FIFO空/满标志的算法。 -FIFO FULL/EMPTY Arithmetic
sfifo
- 牛逼的娴熟的异步fifo,vhdl程序,波形完美-fifo