搜索资源列表
DC_FIFO
- DC_FIFO 是异步fifo
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
FIFO-verilog
- 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
FIFO
- 异步FIFO国外经典教程，包含两篇重量级文献 -Asynchronous FIFO foreign classic tutorials, including two heavyweight literature
fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
fifo
- 基于verilog的fifo异步实现的源代码和分析。-fifo
FIFO
- FPGA实现FIFO模块，用于异步数据处理，作为高速缓冲CACHE-FPGA realization of FIFO module for asynchronous data processing, as the cache CACHE
afifo
- verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
async-FIFO
- 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
FIFO
- 基于fpga的异步FIFO的设计和实现源代码-Fpga-based asynchronous FIFO design and implementation of source code
fifo
- 异步FIFO的VHDL程序，已经通过quartus编译和仿真。 -Asynchronous FIFO, VHDL program, has been compiled by quartus and simulation.
fifo
- 异步FIFO是一种先进先出的电路，使用在需要产时数据接口的部分，用来存储、缓冲在两个异步时钟之间的数据传输。- Asynchronous FIFO is the electric circuit which one kind advanced leaves first, uses when needs to produce data interface s part, uses for to save, the cushion between two asynchronous clock s d
fifo.vhdl
- 异步fifo的vhdl源代码,可实现异步信号的传送-The asynchronous fifo vhdl source code, enabling the transmission of asynchronous signals
FIFO
- 这是关于异步fifo的学习资料，数字系统设计中经常用到fifo模块，了解fifo原理是学会数字系统设计的基础-This is about asynchronous fifo learning materials, digital system design is often used fifo module fifo principle is to learn to understand the basis for the design of digital systems
fifo_vhdl
- 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,