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c22_FIFO.rar
- 精通verilog HDL语言编程源码之8——异步FIFO设计,Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
yibu_FIFO_design
- 异步FIFO实例,精通verilog hdl中的例子,供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码,FPGA采用ep2c5芯片,做成异步fifo,ad芯片采用TI的ths1230,da芯片采用TI的TLV5619,仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
ascfifotestbench
- 自写异步 fifo TESTBench 该fifo对初学者很有帮助!-Since the write fifo TESTBench asynchronous fifo very helpful for beginners!
0917afifo_s
- 采用同步异步信号的方式,将两个CLK统一到同一个时钟下工作,用同步FIFO实现异步FIFO-Asynchronous signals using synchronous way, two a clock CLK to the same uniform to work, using synchronous FIFO Asynchronous FIFO
fifodesign
- 同步fifo设计,与原来上传的异步fifo不同。同步fifo是使用同一个时钟,异步fifo使用不同的时钟域-synchronize fifo design
ASY_FIFO
- 用Verilog编写的异步FIFO,可以方便的实现同步异步的转换,在全局异步局部异步的系统中得到广泛应用-ASY_FIFO written with verilog,and it is very useful in a GALS system
Asynchronous_Resets_FILO
- 外国编程高手关于异步fifo和复位电路的精度论述。-Master a foreign programming asynchronous fifo and the reset circuit on the accuracy of exposition.
yfifo
- 一个异步FIFO,自己写的。初学多交流学习进步快!-An asynchronous FIFO, write your own. Beginners to learn and exchange more rapid progress!
fifo2
- 异步双时钟fifo,vhdl源代码。基本组成是定制的fifo加上空满判断逻辑,基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
memtest
- 在数字系统中,一般存在多个芯片,利用不同的特点用于实现不同的功能,一般都包含CPU,FPGA,AD,DA,memory,ASSP(专用标准模块),ASIC等。CPU用于进行智能控制,FPGA进行硬件算法处理和多设备接口,AD进行模数转换,DA进行数模转换,memory存储临时数据。因此,FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入,数据输出,双向通讯,指令传递,地址管理,不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
FIFOadnVHDL
- FIFO (先进先出队列)是一种在电子系统得到广泛应用的器件,通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。
synchronousfifo
- 采用SystemC语言编写的异步FIFO,非常适合初学SystemC语言的人作为例子练习。-SystemC language using asynchronous FIFO, SystemC is suitable for beginners to practice the language of the people as an example.
sync_fifo
- 这个实现了一个异步的fifo ,通过同步的方法把异步fifo变为同步的fifo来实现,简化了硬件实现的工程-This implements an asynchronous fifo, by synchronizing the asynchronous method into a synchronous fifo fifo to achieve, simplifying the hardware implementation of the project
sdfsdFifo
- 这是一个异步fifo的Verilog 代码,该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
Amin
- 微处理器中异步FIFO的一种优化方法 FIFO Optimization-A microprocessor in the asynchronous FIFO Optimization