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FSM
- 文章介绍的状态机的优化写法，并给出经典实例。使读者更清楚的明了FPGA中状态机的优点，以便工程中的使用。-This paper introduces the optimization of state machines written, and gives the classic example. So that readers understand more clearly the advantages of FPGA in the state machine to the project u
dir3
- VERILOG 语言写的使用状态机实现奇数分频-VERILOG language is written by the state machine to implement an odd number of points frequency
Time_Triggered_system
- 基于51单片机的状态机的多任务处理教你如何写程序很实用 -51 single-chip state machine based multi-tasking to teach you how to write useful programs
State-machine-clock
- 状态机思想写的51单片机驱动的时钟，含ROTEUS仿真文件-Idea to write state machine 51 microcontroller-driven clock, simulation files containing ROTEUS
LQB G7
- 蓝桥杯第七届国赛代码（状态机扫描矩阵键盘、中断数码管显示、软件IIC、片内EEPROM、带DS18B20\DS1302）(Blue Bridge Cup seventh Tournament (state machine code scan matrix keyboard interrupt, digital display, IIC software, EEPROM, chip with DS18B20\DS1302))
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
LabVIEW状态机实用课程
- 介绍labview中常用到的技术——状态机以及附带的相关源码(Describes the commonly used technology in LabVIEW - state machine, as well as the associated source code)
状态机
- 简单的状态机，按下按钮可在4个状态间进行切换(simple state machine)
jiaotongdeng
- 基于VHDL状态机的交通灯设计（已仿真下载实验板测试）(Traffic light design based on VHDL state machine (simulation download, experimental board test))
C language state machine
- C语言状态机 用状态机原理进行软件设计 摘要：本文描述状态机基础理论，以及运用状态机原理进行软件设计和实现的方法。 关键词：有限状态机 层次状态机 面向对象分析 行为继承(C language state machine)
Microsoft.Activities.StateMachine
- 使用window状态机实现简单的请假审批流程(Use state machine to achieve approval process)
一段式有限状态机
- 通过找hello结束后，控制led的翻转(After you look for Hello, control the LED flip)
design
- 使用有限状态机完成序列检测，是FPGA开发中的基础程序(sequence detection with state mation)
state_machine
- 同样是简单的MAX II编程，状态机顾名思义，0到8的循环显示，用到了数码管。(The same is a simple MAX II programming, the state machine as its name suggests, 0 to 8 of the cycle display, using the digital tube.)
Mealy_TrafficLight
- 基于FPGA交通控制器的Mealy状态机实现(Mealy state machine controller based on FPGA traffic)
simple state machine
- 使用labview开发环境，对经典状态机功能完成实现(simple state machine)
FiniteStateMachine
- 一个可以识别正则表达式的状态机，采用了多种Case描述，方便修改(A finite state machine designed for identifying expression patterns)
4
- 设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额5元，并支持找零。要求： （1）用状态机方法设计；(Design an automatic rail transit ticketing circuit, accepting only 1, 2, 5 yuan, 5 yuan per ticket, and support change. Requirements: (1) design with state machine method;)
状态机
- 设计一个简单的数字电路用于电子卖报机，要求如下： 报纸价格为1.5元；投币器只接受5角和1元硬币；投币器不找零。当投入金额合适时，报纸出口打开，否则关闭。用Verilog完成设计。(The design of a simple digital circuit for electronic selling machine, the following: The price is 1.5 yuan; the coin only accept 5 cents and $1 coin coin do
fsm3
- verilog状态机实验，说明一个状态机的生成过程(Verilog state machine experiment, which illustrates the generation process of a state machine)