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eclock
- MAXPULS II 下VHDL实现多功能电子钟的源代码,包括时钟,秒表,日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
EDA_miaobiao
- 《数字电路EDA入门-VHDL程序实例》---数字秒表程序例子-"digital circuit EDA portal-VHDL program examples" -- digital stopwatch procedures example
byvhdstopwatchl
- 1.高精度数字秒表(0.01秒的vhdl语言实现) 2.具有定时,暂停,按键随机存储,翻页回放功能; 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔,可控性高。 5.模块化设计,其中的许多函数可以成为vhdl语言的通用经典例子(包含分频电路设计,动态扫描时钟设计,译码电路设计,存储器设计,存储回放显示设计)-1. High-precision digital stopwatch (0.01 seconds vhdl la
VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT,带源码,解释详细,一步一步学习,是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
b
- 基于VHDL的数字时钟设计与实现。。。。可以实现时钟,秒表-VHDL-based Design and Implementation of Digital clock. . . . Can achieve clock, stopwatch. .
vhdl
- 基于fpga的vhdl语言,芯片是ep2c8系列,此代码实现的是秒表显示,毫秒到分的数码管显示,数码管是共阳的,分模块设计的,-The vhdl fpga-based language, the chip is ep2c8 series, this code is implemented stopwatch showed milliseconds to-point digital control, digital control is a total of Yang, the sub-modul
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例,仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码(加/减)计数显示器(ADD-SUB)。 二、指示灯循环显示器(LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可
5
- 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
3
- 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K
vhdl-dianziwannianli
- 基于FPGA的电子万年历,此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calen
Digital-stopwatch-design
- 数字秒表的设计报告,用VHDL语言编写程序,实现分析讨论中各种功能,分别进行编译并生成相应的模块,然后将这些模块连接起来形成电路图,并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the correspo
VHDL-multi-function-clock
- 多功能时钟,包括一个时钟和一个秒表,可以互相切换并且不过中断各自的运行-a multi-function clock
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序,比如FIFO,秒表,数字钟,七段数码管,状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
timer
- 自己做的计时秒表VHDL语言程序,运行良好,一切俱全。-Own stopwatch VHDL language program, run good, all taste.
VHDL-stopwatch-reports-and-code
- 用VHDL实现数字秒表的设计实践,并用FPGA下载进行功能验证!-Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
stopwatch-VHDL
- 自己用VHDL语言写的一个秒表程序,包括秒,分秒和百分秒。有程序说明和VHDL代码,一看就懂-Own use VHDL language used to write a stopwatch program, including the seconds, minutes and seconds and hundredths of a second. There descr iption of the procedures and VHDL code, one can understand
stopwatch-based-on-VHDL
- 基于VHDL的电子秒表的设计,使用VHDL语言描述一个秒表电路,利用QuantusII软件进行源程序设计,编译,仿真,最后形成下载文件下载至装有FPGA芯片的实验箱,进行硬件测试,要求实现秒表功能。-Design of electronic stopwatch based on VHDL
ELECTRONICCLOCK
- VHDL语言设计的电子钟,并且有暂停功能和清零功能的按键实现,并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
szmb
- 用VHDL语言基于ISE,在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)
课程设计-数字钟
- 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)