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miaobiao
- 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
vhdl_miaobiao
- 基于FPGA，VHDL实现秒表功能，利用了分频和计数-FPGA, VHDL-based stopwatch function, the use of divide and count
A-stopwatch-based-on-FPGA
- 基于FPGA的VHDL语言编写的秒表的源程序，需要在FPGA的平台下进行仿真。-A stopwatch written in VHDL language based on FPGA
Digital-stopwatch
- 1、了解数字秒表的工作原理。 2、进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、掌握VHDL编写中的一些小技巧。 -1, to understand the working principle of digital stopwatch. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the t
miaobiao
- 利用vHdl描述语言实现的60秒秒表。能够实现60秒的计时功能-Use of vHdl descr iption language implementation 60 seconds stopwatch
seconds-counter
- 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count
Example23
- 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
secnew
- 基于FPGA的数字秒表设计。用VHDL语言设计数字秒表。-FPGA-based design of digital stopwatch. Design using VHDL digital stopwatch.
timer
- 基于VHDL语言的一个简单秒表，包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards
shuzizhong
- 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
exp18
- 这是一个vhdl的交通灯程序，可以实现两个方向间红、黄、绿灯之间的亮灭转换，同时还有秒表的计数、显示功能，为学习vhdl的人提供一定的技术参考。-This is a vhdl traffic lights procedures can be achieved between the two directions of red, yellow, green light off between the conversion, as well as the stopwatch count, displ
MB
- 基于VHDL语言数字秒表设计,在FPGA实验平台下开发-Digital stopwatch design based on VHDL, FPGA experimental platform under development
jishu
- 基于VHDL的计时秒表 59分59秒59 具有计时暂停功能 通过数码管显示-Timing stopwatch 59.59.59 with timing suspended through digital tube display please enter the text to be translated
JiShuQi
- 实现了一个秒表计数器，输入为2MHZ时钟，使用VHDL语言实现-It implements a stopwatch counter input 2MHZ clock, using VHDL language
miaobiao
- 使用VHDL\FPGA实现秒表的设计，包含所有源码。-Use VHDL\FPGA to achieve a stopwatch
stopwatch
- VHDL秒表设计，硬件环境为NEXYS4开发板，有暂停功能，7段数码管显示。-VHDL stopwatch design, the hardware environment for the NEXYS4 development board, a pause function, 7 digital tube display.
stopWatch
- 基于VHDL语言数字秒表的实现！使用模块化的设计，包含详细设计说明文档。可在DE2-115开发板上进行验证！-digital stop watch based on VHDL language
VHDLstopwatch
- 采用vhdl硬件描述语言实现的秒表计时器程序源码及顶层电路设计图，实现了计时器，数码管显示，按键控制及蜂鸣器等功能-Using VHDL hardware descr iption language to realize the stopwatch timer program source code and top-level circuit design, the timer, digital tube display, control buttons and a buzzer functio
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
clock
- 本个程序主要通过vhdl来实现一个秒表的设计-This procedure mainly through the VHDL to achieve a stopwatch design