搜索资源列表
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
Based-on-51-stopwatch
- 基于51单片机的秒表设计，包括跑表、闹钟、秒表等功能，内容齐全，完全可以运行-51 microcontroller stopwatch design, including a stopwatch, alarm clock, stopwatch, and other functions based on content complete, fully operational
Multifunction-Clock
- 基于51单片机的电子钟设计，具有跑表、调表、秒表、年月日等功能，本人自己原创作品，完全可以运行-51 microcontroller based design electronic clock, with stopwatch, transfer table, stopwatch, date and other functions, my own original works, can be run
paobiao
- verilog实现数码跑表，基于ALTERA DE2—70开发板实现验证，其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.
clock171
- 电子时钟，能够进行计时，可设定闹钟，可以当做跑表，并且可以更改时间-electric clock
DFWR321436REYHGFH
- STM32项目实战之RTC跑表功能实现代码,对于初学者来说，是有非常的帮助效果的-RTC stopwatch function STM32 project combat the realization of the code, for beginners, it is very help effect
VHDL_paobiao
- 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
danpianjishizhong
- 电子时钟，基于51单片机，和1602液晶显示屏，正常走时，闹钟，跑表-Electronic clock, based on 51 single chip microcomputer, and 1602 LCD screen, normal walking, alarm clock, stopwatch
shuzipaobiao_all
- VErilog源码，数字跑表数码管显示，按键控制-VErilog source, digital stopwatch digital display, control buttons
dig_watch
- fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
4.9.4
- 基于8086汇编语言中使用8253A定时/计数器设计跑表。-Based on the 8086 assembly language using the 8253A timer/counter design run the table.
paobiao
- 使用verilog实现跑表计时功能,已经验证过，能够实现功能-Use verilog to achieve run time function
ARM7
- 基础程序，基于lpc2000系列，对ARM7初学者很有帮助，内含protues仿真电路图(Basic procedures, based on the lpc2000 series, useful for beginners ARM7)
paobiao
- 此上传的是在FPGA的spartan 3e系列开发板上面实现精准到 时、分、秒、百分秒的数字跑表的Verilog源代码。(This is uploaded on the FPGA Spartan 3E series development board to achieve precise time, minute, seconds, 100 seconds of digital stopwatch Verilog source code.)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例