搜索资源列表
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
binarydivider
- matlab编写的二进制除法器，能够实现64位除法运算-matlab write binary divider, the division can achieve 64
SDivider16bit_V120
- 循环型除法器Verilog代码，带有8位小数，可使除法器固定长度，缩减时钟开销-Streamlined divider Verilog code, with eight decimal places, make fixed-length divider, reducing the overhead clock
div
- vhdl除法器 vhdl除法器 vhdl除法器 -divider vhdl vhdl vhdl divider divider divider vhdl vhdl vhdl divider divider
vfxc
- 一种实用的除法器,对于初学者很大帮助，代码不大，精简好用。-A practical divider, very helpful for beginners, the code is not streamlined easy to use.
IntegerDivider
- 整数除法器 无负数复数 期末项目 verilog-integer divider
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
divider
- 主要是基于VHDL的五位除法器设计，基于eda试验箱的设计。-Five main divider VHDL-based design, based eda chamber design.
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
Design-of-divider
- 除法器设计在FPGA板上的应用 除法器设计在FPGA板上的应用-The application of FPGA in design of divider class.
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
my_32fp_mult
- 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
myfpga
- 这个是经典的FPGA的相关的乘法器，除法器的代码，还有别的可用的资料，都是网络上攒的，并且真的是非常经典-This is a classic of the relevant multiplier divider FPGA code, as well as other available information, are saved on the network, and really is very classic
multiplieranddivider
- 乘法器和除法器的VHDL实现方法,可运行，占用逻辑资源少。-VHDL descritpion about muiltiplier and divider