搜索资源列表
8b_10b
- vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous act
8b10b_encdec.rar
- 8b10b转换编码、解码verilog源代码,8b10b transcoding, decoding verilog source code
8B-10B.rar
- 一种新的8B-10B编解码硬件设计方法，希望对您的工作有所帮助。,A new codec 8B-10B hardware design, and I hope to be helpful to your work.
16b20b_Encoder
- VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
tlk1221jiaoyan_k
- 采用8B/10B编码方式，以不同的模式插入K28.5码进行数据校验，验证tlk1221芯片的数据传输是否正确，观察收发数据是否一致。-To check the data which is transceived by the way of 8B/10B coder/decoder by asserting K28.5 code in different mode and to observe that whether these data have been missed in the tran
8b10b
- 8b10b转换编码的verilog描述，非常好-8b/10b trans
uart
- 本程序的功能是实现串口通信，采用232传输协议，编码方式为8B/10B转换，即一位起始位，8位数据位，一位停止位，在actel Fusion系列开发板上得到验证，具有很强的通用性。本程序的编程语言为Verilog.-This procedure is to achieve the functions of serial communication, the transfer protocol is 232.The encoding protocol is 8B/10B , that is, a
16b20b_Decoder
- VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading
MEdia_control_i2c
- 将来自MAC的GMII8B码进行8B/10B编码。FPGA输出10路10B码的数据，如有必要，可配置外挂SDRAM，FPGA还得实现SDRAM控制器，-Will come from the MAC' s GMII8B codes 8B/10B encoding. FPGA output 10 Road 10B code data, if necessary, can be configured to plug SDRAM, FPGA have to realize SDRAM contro
ENCODE_8B_10B
- 8B-10B编码，Verilog代码，通过编译，仿真，代码规范，清晰-8B-10B code, Verilog code, through the compilation, simulation, code specifications, clear
8b10b_encdec_latest.tar
- 8b-10b used in high speed communication-8b-10b used in high speed communication
8B10B_decode
- 介绍8b/10b的编码与解码的详细流程，主要是基于FPGA的实现方法-8b/10b encoding and decoding described the detailed process
top_8b_10b_code
- 光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信 号
8b10b
- 8b/10b编解码模块，VHDL语言设计，经过编译，里面有测试平台以及文档。不可错过哦！-The 8b/10b encoding and decoding modules, VHDL language design, compilation, there are test platforms, and documentation. Not miss it!
8b10_enc
- 8B10B是应用最广泛的编码技术。它被用于串行连 接SCSI、串行ATA、光纤链路、吉比特以太网、XAUI（10吉比特接口）、PCIExpress总线、InfiniBand、 SeriaRapidIO、HyperTransport总线以及IEEE1394b接口（火线）技术中。-8b/10b has been widely adopted by a variety of high speed data communication standards used today and should
b8b__10bbi
- vhdl开发，8b—10b 编解码器设计Encoder: 8bb/10b Encoder (file: 8b10b -vhdl development, 8b-10b codec design Encoder: 8bb/10b Encoder (file: 8b10b
8B10B
- 8b/10b编解码实现，很实用。可以借鉴-8b/10b encoding and decoding to achieve, very practical. Can learn
8b10_enc
- This program is used to do encoding according to 8B/10B protocol. The program has been written in VHDL
encode_8B10B
- 用verilog编写的8B/10B编码模块。参考了网上的源码，并取消了时序，以纯逻辑实现。将3B/4B、5B/6B两部分单独写成模块，可读性更强-Using verilog 8B/10B encoding module. Online reference source, and canceled the timing, pure logic implementation. The 3B/4B, 5B/6B written two separate modules, more readable
8b10b-master
- 8B/10Bencode and decoder