搜索资源列表
aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
FPGA
- 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
aesencryption
- Aes encryption on Fpga
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
8_Code
- AES algorithm encryption and display on FPGA spartran 2e
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
AES-implementation-based-on-FPGA
- 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
AES
- FPGA Implementation of AES Encryption and Decryption
aes
- AES FPGA verilogHDL实现(AES hardware implementation)
aes-project-master
- aes project vhdl FPGA
AES加密_解密_verilog代码
- 用Velirog语言实现AES加密解密，可在FPGA上实现(AES encryption and decryption in Velirog language)
各种密码算法的FPGA实现情况
- 各种密码算法的FPGA实现情况 1.AES算法FPGA实现分析 2.DES加密算法的高速FPGA实现 3.RSA加解密运算的FPGA硬件实现研究(FPGA implementation of various cryptographic algorithms)
基于FPGA的AES256位加密
- aes 256位 算法 加密程序，使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)