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63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
AES
- 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
aes_-vhdl
- aes encription coding in vhdl language
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.