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Altera_LM75_test
- 周立功的FPGA ARM 51的板子上的温度传感器，本样例基于FPGA用Verilog写的。-Ligong weeks of the FPGA ARM 51 temperature sensors on the board, the FPGA-based sample written using Verilog.
icache
- ARM9指令Cache缓存模块的Verilog代码-cache verilog for ARM
arm7
- 基于arm-v4架构，兼容ARM7指令集。附录有说明文档，希望对大家有用。可以在windows上使用Debussy+modelsim的组合开发，是Verilog写的-Based on arm-v4 architecture, compatible with ARM7 instruction set. Appendix have documentation, we hope to be useful
sARM01_07_12_2
- verilog hdl实现的ARM处理器-ARM processor implement by verilog HDL
AMBA
- AMBA总线的verilog实现，AMBA是ARM limited 公司推出的一种为嵌入式系统所设计的总线协议。-AMBA bus Verilog, AMBA bus protocol is the the of ARM limited company launched a embedded system design.
Robust and Optimal Control by Kemin Zhou
- Embeded-SCM Develop ARM-PowerPC-ColdFire-MIPS Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-FPGA-Verilog Other Embeded program
cpu
- 用system verilog写的一个arm处理器原代码。-Write an ARM processor system verilog source code.
a_vhd_16550_uart_latest.tar
- vhdl-fpga-c++-c-wireless networks-linux-verilog-cpld-arm-dsp
UART
- 用verilog编写的UART串口通信程序，经验证误码率为0，系统由ARM控制FPGA的串口进行通信；-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
ARM_37numbers_32bits
- ARM架构下的32位37个寄存器组的verilog源码-ARM architecture 32 37 register banks verilog source
ARM_shift_32bits
- ARM架构下的32位桶形移位器的verilog源码-32-bit barrel shifter verilog ARM architecture of the source
MIPS_shift_8bits
- ARM架构下的8位桶形移位器的verilog源码-8 barrel shifter ARM architecture of verilog source
fsmc
- 修改过的icore2复用模式ARM与FPGA FSMC接口 Verilog的-Modified icore2 multiplexed mode ARM and FPGA FSMC Interface Verilog s
rtl_1795
- Developper:mathswork Arm IP Core Verilog This IP core is an ARM clone. It has the same architecture of ARM v4. Its main feature lists: Not support coprocessor instructions Not support THUMB instruction set All interrupts
FIFO1
- 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据 (FIFO的宽度：也就是英文资料里常看到的THE WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以
arm_cache_sort
- ARM高速缓存(Cache)Verilog代码-ARM Cache Verilog
AMBA
- AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave