搜索资源列表
DE2_70_VGA_pattern_gen
- 用纯Verilog语言在DE2-70开发板上实现彩色条纹的输出-The colored stripes output Verilog language pure DE2-70 development board
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
VGA
- 用Verilog HDL编写的VGA显示程序，可实现图像的显示，在DE2-70上测试通过，有很大的参考价值。-Prepared using Verilog HDL VGA display program, image display DE2-70 test by great reference value.
uart
- 用Verilog HDL编写的串口输入输出程序，可实现数据的传输，在DE2-70上测试通过，有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序，在DE2-70上测试通过，有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
DE2_pin
- DE2控制面板 液晶显示验证代码 用verilog 语言描写的-this is a control panel about LCD s display expierents
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
my38decoder
- 这个是用verilog语言写的一个38译码器的程序，在DE2最小系统板里验证过 -This is to use verilog language is written a and decoder program, in DE2 minimum system board validated
led_decoder
- 这个是用verilog语言写的一个点亮LED灯的程序，在DE2最小系统板里验证过-This is to use verilog language written by a light LED lights program, in DE2 minimum system board validated
counter
- This is 2-BCD numbers Counter on board Altera DE2 Code Verilog HDL (You must import DE2_pin_assignments.csv to use this code)
miaobiao
- 这是用verilog写的一个关于秒表实现的程序，已在DE2上成功实现-Verilog write a stopwatch to achieve the program has been successful on the DE2
Timer
- 用verilog语言实现的定时器。在DE2-70开发板上设计，七段数码管分别用于显示时/分/秒，并带有预置时间功能。-Timer verilog language. DE2-70 development board design, seven-segment digital tubes were used to display hours/minutes/seconds, with the function of the preset time.
another
- 这是一个用数码管显示的verilog语言描述的数字秒表，且引脚已经分配完毕，基于DE2，可直接下载到板子上使用-This is a digital stopwatch with digital display verilog language described, and the pins have been fully allocated, based DE2, can be directly downloaded to the board
count60
- 基于de2板的数字计时器，使用verilog hdl 语言。很好的新手教程-Based on the the the de2 board digital timer, the use of verilog hdl language. Good newbie tutorial
texi
- 出租车计费器。verilog语言设计，合理利用了de2开发板资源，功能全面-Taxi meter. verilog language design
jiaotongdeng
- Verilog编写的交通灯程序，Altera公司的DE2开发学习板。-Verilog prepared by the traffic lights program, Altera' s the DE2 development of learning board.
chuzuche
- Verilog编写的出租车计价程序，Altera公司的DE2开发板环境中。-Taximeter program written by Verilog, Altera' s DE2 development board environment.
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
DE2_70_TV
- de2 70 开发板的演示程序，verilog语言编写，视频输入输出-de2 70 development board demo program, verilog language written, video input and output