搜索资源列表
PWM
- 用Verilog编写的PWM产生器,已经在cyclon DE2板子上测试通过,建议用Quartus 10.1综合。-PWM generator using Verilog.
SoftDrink
- 用Verilog编写的自动售货机控制程序,在cyclon DE2开发板上测试通过,建议用Quartus 10.1编译。-Vending machine control program written using Verilog test by in cyclon DE2 development board, we recommend using Quartus 10.1 compiler.
DE2_115_Audio
- DE2-115开发板音频录放verilog HDL代码-DE2-115 development board audio recorders verilog HDL code
DE2_115_NIOS_DEVICE_LED
- DE2-115开发板的LED灯设计 Verilog HDL语言编写-DE2-115 development board LED lamp design Verilog HDL language
DE2_115_NIOS_HOST_MOUSE_VGA
- DE2-115开发板的verilog HDL的VGA设计-DE2-115 development board VGA verilog HDL design
DE2_115_PS2_DEMO
- DE2-115开发板的PS2的Verilog HDL语言设计-The DE2-115 development board of the PS2 Verilog HDL language design
SDRAM
- 用Verilog HDL语言编写的SDRAM控制器,在DE2-70的开发板上实现。-SDRAM Controller with Verilog HDL language, DE2-70 development board.
Counter_10
- verilog 计数器,每计数到十清零,可以直接下载到DE2-70开发板-verilog counter
project1
- 4比1多路选择器,HDl verilog语言编写,能在DE2上运行-4 to 1 multiplexer, HDl verilog language, able to run on the DE2
project2_1
- 3:8译码器,HDl verilog语言编写,能在DE2上运行-3:8 decoder, HDl verilog language, able to run on the DE2
project2_2
- 7段译码管,用于显示数字,HDl verilog语言编写,能在DE2上运行-7 segment decoder tube used to display numbers, HDl verilog language, can be run on the DE2
project3_1
- 逐次进位加法器,HDl verilog语言编写,能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
project4_1
- D触发器门级实现,有异步复位置位,HDl verilog语言编写,能在DE2上运行-D flip-flop gate-level implementation, there are asynchronous Reset_Set, HDl verilog language, able to run on the DE2
pinpongf16
- FPGA Verilog程序 采用DE2-70 Altrer 实验班实现小球跳动-FPGA Verilog program using DE2-70 Altrer experimental class of small ball beating
VGA1
- 基于ALTERA DE2 开发板开发的VGA外接屏Verilog显示程序。-ALTERA DE2 development board based on the development of Verilog VGA external screen display program.
DE2_70_VGA_only
- de2-70 开发板上的bga驱动,用VERILOG写得,希望对大家有用,这个随意显示几个彩条。-de2-70 development board bga driven, with VERILOG written, we want to be useful, this random display several color bars.
jiaozhi
- 完成通信系统中数据交织器的设计的设计,要求用Verilog HDL编程,在DE2平台上实现,在示波器上显示观察。-Complete data communication system Interleaver Design for the design, requirements using Verilog HDL programming, implemented on the DE2 platform, observed on the oscilloscope display.
DE2_Top
- 此设计是一个裸机的设计,其中包含在DE2开发板所有的引脚分配。它还包含一个与所有的对应于每个引脚的输入/输出端口的Verilog模块。这可以被用来作为一个起点上的电路板的设计。-This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output por
gaus_filter
- This Gaussian filter is implemented by Verilog HDL and successfully simulated on ModelSim. Besides, it has been implemented on Altera DE2-70 board
pingpongf16
- 使用quartusii软件,用verilog语言编写,通过DE2-70板在屏幕上实现乒乓球动态效果。-Use quartusii software, using verilog language, through the DE2-70 board on the screen to achieve tennis dynamic effects.