搜索资源列表
FIFO
- Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
FIFO
- vhdl code for first in first out
FIFO
- a fifo designed in vhdl. this fifo is implemented in a different way, using access type.
FIFO
- 基于vhdl语言的fifo设计，方便你了解先进先出理论-Based on the the vhdl language of fifo design, allowing you to understand the first-in, first-out theory
fifo
- 先进先出存储器的接口设计，采用VHDL语言-FIFO memory interface design, using VHDL language
FIFO
- FIFO在VHDL上的实现。没有注释，较为完善，已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
FIFO
- FIFO的资料，包括文档说明已经一个VHDL文件。-FIFO data, including document describes a VHDL file.
fifo
- This VHDL code for FIFO that is used in a NOC router-This is VHDL code for FIFO that is used in a NOC router
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
FIFO
- 实现FIFO（先进先出）存储器设计,用VHDL实现 -to implement the FIFO meoney
aFifo
- Function : Asynchronous FIFO VHDL CODE
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
VHDL-memory
- 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
FIFO
- FPGA内部FIFO存储器设计的vHdl源代码-FPGA internal FIFO memory design vHdl source code
SLAVE-FIFO-8BITS
- EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
3333333
- 基于vhdl语言的同步fifo的宏模块调用程序，可学习fpga的宏模块调用方法-Synchronous fifo vhdl language-based macro block the calling program, can learn fpga macro module calls methods
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
Asynchronous-FIFO
- Asynchronous FIFO Implementation in VHDL
fifo
- 设计一个同步的双端口fifo ,大小为8*128。-Designing a synchronous dual-port 8* 128 fifo using VHDL.
FIFO
- 用VHDL语言实现一种异步FIFO，并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.