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FIR_chanbing
- 串并结构的FIR滤波器,Verilog语言编写，希望对大家有帮助-String and the structure of FIR filter, Verilog language, we want to help
fir_filter
- 一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
LPF
- 数字低通FIR滤波器Verilog实现代码-Verilog digital FIR filter implementation code
firlms
- 基于FPGA的自适应FIR滤波器的verilog设计与实现-Adaptive FIR Filter Based FPGA Design and Implementation of verilog
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
fir_filter_generator
- FIR有限冲击响应滤波器verilog代码和测试-FIR finite FIR filter verilog code and test
8_oeder_signed_parellel_DA_FIR
- 本程序使用Verilog编写的程序。 本例是1个8阶对称系数的FIR滤波器，采用并行分布式算法。输入位宽为12位，输入是有符号的，即有正有负。-it s a program with Verilog
firfilt
- FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
TverilogFIRh
- 基于verilog的FIR滤波器程序设计（调试过的的）-verilog ， -Verilog program of FIR filter design (debug)-Verilog,
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
FIR_lowpass
- FIR 滤波器 verilog 语言编写 很实用-FIR filter design
da_fir
- 基于verilog的分布式算法FIR滤波器 有两个文件 一个用来生成查找表-FIR filter using Distributed Algorithm.
my_fir
- Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
FIR_Lowpass
- 用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
filter
- verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(F
filter_signed_and_unsigned
- FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
proiect
- Fir filter implemented in verilog and tasted. also conteins the implementation in simulink