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uart_tx_rx
- 在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。-Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debuggi
Verilog-RS232
- 本程序是在FPGA里面模拟RS232串口，并在已调试成功。-This procedure is simulated in FPGA RS232 serial port, and in the debugging success
uart_rx_module24
- UART serial interface communication based on FPGA, this modular by receiving PC serial port data (8), converted into parallel 24 data output
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
uart
- 串口通信时初学FPGA者必须要掌握的基础知识，这里给出了UART通信的VHDL代码，以及仿真测试文件。-A serial port communication beginner to must master the basic knowledge of FPGA, UART communication VHDL code is given here, and the simulation test files
uart
- 基于verilog语言，使用FPGA对串口功能进行模拟与实现-Based verilog language, use the serial port function simulation and FPGA implementations
PS2
- FPGA外部PS2j键盘部分代码，FPGA芯片采用xilinx sptan3e 可以实现键盘与串口的通信-The FPGA external PS2j keyboard part of the code, the FPGA chip using xilinx sptan3e can realize the keyboard and a serial port communication
uartfifo
- FPGA简单应用，VHDL程序，串口UART驱动程序，供学习参考。-FPGA and simple application, VHDL program, UART serial port driver, provide the reference for the study.
ps2keyboard
- FPGA通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。 实验时，需要接键盘，还要用调试助手，下载程序后，在键盘上按下一个键，比如A，则在PC调试助手上可看到A-FPGA through PS2 receive keyboard data, and then receive the letters A to Z conversion keys corresponding ASII code, through the serial port t
UART_proj
- 串口发送接受功能，上位机发送消息给FPGA，FPGA接收后将相同的消息发送至上位机。-A serial port to send in function, PC sends a message to the FPGA, FPGA after receiving the same message is sent first place machine.
232controlsend
- 通过串口发送帧命令来控制FPGA发送429信号，并通过429板卡接收验证。-Through the serial port to send the command to control the FPGA send 429 signal, and through the verification of the board.
232controlrecieve
- 通过串口发送帧命令控制FPGA接收429板卡发送的信号，并点亮相应LED。-Through the serial port to send the command to send the FPGA to receive the 429 card board to send the signal, and light up the corresponding LED.
232control429
- 通过串口发送不同的帧命令控制FPGA分别发送和接收429信号。-Send and receive 429 signals through the serial port to send different frame command control FPGA.
scope_new
- 本实验，为 ZX-2 开发板的综合实验，该实验利用 ZX-2 开发板上的 ADC、独 立按键、 UART 等外设， 搭建了一个具备丰富功能的数据采集卡， ZX-2 开发板负 责进行数据的采集并将数据通过串口发送到 PC 机上， PC 端，利用强大的串口调 试工具——串口猎人，来实现数据的接收分析，并将数据分别以波形、码表、柱 状图的形式动态显示出来，以让使用者能够直观的看到 ADC 采集到的信号细节。 同时，用户也可以使用串口猎人通过串口给下位机（ FPGA） 发送指令，下位
uart_lcd_display_XUP
- Uart串口通信程序，PC机向FPGA的串口发送数据，FPGA的串口收到数据后回传到PC机，同时显示在lcd屏。-Uart serial communication program: The serial port of PC sends data to the FPGA. After the serial port of FPGA receives the data, FPGA sends the received data back to the PC, simultaneously dis
5_bluetooth_uart
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
vhdl
- 利用vhdl语言实现（7,4）汉明码编码过程，在FPGA上实现，并且通过串口发送个计算机，在计算机上显示。-Use vhdl language (7,4) Hamming code encoding process, implemented on the FPGA, and send a computer through the serial port, the display on the computer.
TX_RX
- FPGA用verilog实现串口和电脑的字符串以及单字符精准无误通信，即通过电脑向FPGA发送任一长度数据，FPGA返回PC相同的数据。波特率为9600，本例程为了得到精准的波特率使用了50M时钟的3倍频，测试可用，如有不明的地方，可以给我留言-FPGA implementation using verilog string and the computer serial port and single-character accurate communication, 9600, FPGA u
SDRAM_96M
- 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
SCH
- DTMB GB20600-2006 terrestrial dig FPGA or CPLD reads the SD card IP tell us how to divide frequency f UMC 90nm design models. please re UMMC 90nm models. Please read the Bluetooth serial port via the pho scope FPGA code AG 0.35u