搜索资源列表
downstream_pipeline
- Altera NIOS II 软核的downstreampipeline-downstreampipeline in NIOS II
CFI_FLASH
- Altera NIOS IICFI 驱动-cfi driver in NIOS II
Introduction_to_the_Altera_SOPC_Builder
- This file contains basics information how to use Altera and NIOS II processor
MyC2Board_RS232_Test
- 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中,用Qsys建立了一个NIOS II为核心的CPU系统,并挂接了一个RS232接口。 在software目录下,有三个工程,一个是用C++类包装的RS232类的Eclipse工程,一个是不用C++类包装的Eclipse工程,还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上,与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个
UART_FOR_Altera
- 用于控制3个独立的全双工传输的UART/RS232接口。该接口由Altera SOPC 实现,开发环境为NIOS II。在Statrix II上工作正常。 每个接口可独立配置为短数据模式和数据流模式。-This C source file is used for controling three UART/RS232 interfaces . These interfaces are implemented by Altera s SOPC module , assembled in a S
RS232
- (6)实验6:串口通讯实验,完整的设计工程文件在RS232文件夹下二、运行环境 程序在以下环境调试通过: (1)Windows XP; (2)Altera公司的Quartus II 8.0 for windows; (3)Altera公司的Nios II 8.0 IDE for windows; (4)Mentor公司的ModelSim SE 6.0;-(6) (2) Altera Corporation Quartus II 8.0 for windows Exp
stepmotornios
- Altera SOPC系统和Nios II处理器实现的一个简单的步进电机驱动系统。
nios_ii-irq
- ALTERA FPGA 构建nios ii CPU ——中断法定时器 本例子教你学会FPGA NIOS中断,熟悉中断,逐步深入。-ALTERA FPGA build nios ii CPU- to interrupt method timer this example teach you to learn to FPGA NIOS interrupt, familiar interrupt gradually deepened.
PC2NIOSII_uart
- Altera Nios II 串口相关程序-Altera Nios II serial program
FA161-SCH
- 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6,FA161板载有SDRAM,SRAM,FLASH方便制作各种应用,开发板所带资料中包括了上位机与开发板USB通信,上位机与开发板以太网通信,上位机与开发板串口通信例程。FA161板载有USB 1.1,USB 2.0(CY7C68013A)接口,以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发,可以进行nios ii程序开发,可以结合MATLAB制作DSP Builder应用。FA
DE2_SD_Card_Audio
- DE2 SD player that uses VHDL and NIOS II to program the DE2 ALtera FPGA board
NiosLED
- 基于NIOS II的数码管显示程序,采用altera的EP2C8Q208芯片。-Digital display based on nios II ,using altera s EP2C8Q208 chip
DE2_NET
- altera DE2开发板和网络通信的例程,使用了nios ii系统-altera DE2 development board and network communication routines, using nios ii system
IrDA
- DE2开发板所付实例,红外无线通信IP核,嵌入式IP核。-altera nios II
VGA
- VGA video controller for the Altera Nios II Processor v4.0
DE2_NET
- Altera的DE2开发板上关于DM9000A的Demo,做好的IP核,在Nios II下运行-Altera s DE2 development board Demo about DM9000A, include IP core, and running under Nios II
CFI_FLASH
- Altera NIOS IICFI 驱动-cfi driver in NIOS II
PSG
- Altera NIOS II 使用的 AY-3-8910 模組 . 包含 AY-3-8910 Verilog code, SOPC builder使用的hw_tcl及R-2R DAC 電路-AY-3-8910 module for Altera Nios II. verilog source code, hw_tcl file and R-2R DAC schematic.
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is