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数字锁相环设计源程序
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input freque
easy_pll
- 锁相环设计文档和一个可执行文件-PLL design documents and an executable file
plltips
- 技术文章《采用PLL设计时需注意的问题》在工程设计中有参考价值-technical article, "using PLL design attention to the problem" in engineering design reference value
PLLDesignAssistant
- PLL design assistnat-- tells you how to design a good P
数字锁相环
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency.
FPGA-global-clk-design-
- FPGA的全局时钟应该是从晶振分出来的，最原始的频率。其他需要的各种频率都是在这个基础上利用PLL或者其他分频手段得到的；因为全局时钟需要驱动很多模块，所以全局时钟引脚需要有很大的驱动能力，FPGA一般都有一些专门的引脚用于作为全局时钟用，他们的驱动能力比较强-FPGA' s global clock should be divided out from the crystal, the frequency of the most original. Other needs of the
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
setup_pll_design
- PLL design assitant, from M.H.Perrott, MIT
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码，对频综和锁相环的设计很有帮助；-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
matlab1
- 61549798pll_matlab[1]课程设计做的PLL,里面有关线性和非线性的都有,大家可以-61549798pll_matlab [1] course design done PLL, on the inside of both linear and nonlinear, we can
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
adsx
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
Hittite-PLL-Design-Installer-v1p1
- Hittite公司以创新的设计使得其PLL产品性能优异，在相位噪声，杂散方面有着卓越表现，其芯片的高集成度使得外围电路简单，设计方便。所以随着电子技术的发展，对频率源的相位噪声性能要求越来越高，Hittite的低相位噪声PLL，在物理、天文、无线电通信、雷达、航空、航天以及精密计量、仪器、仪表等各种领域里都将大有用武之地。-The Hittite companies with innovative design makes the PLL excellent product performan
412039
- filter adf pll design
486520
- altium designer pll design