搜索资源列表
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
simulink_communicationsystems
- 文件中包含有AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM和Delta Modulation的simulink环境下的实现 -This project allows you to learn the communication systems in greater depth by giving you the reins to play with it ! It contains the simu
dean_banerjee_pubns_-_pll_performance_simulation_
- PLL design and simulation
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
StaticPLL
- 介绍FPGA中数字锁相环的设计方法和应用的文档-Introduction of Digital Phase-Locked Loop FPGA design methodology and application documents
AN177
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
AN178
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
an535
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
AN5355
- Digital PLL design, all technic how to develope eficiency digital locked loop. All descr iptions in English in details and examples
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
140401S3C2450_16_51_Power_Design_Guide_Rev03
- This document describes S3C2450/16/51 power design guide for circuit designer. It shows as follows, - recommend DC operating conditions - recommend system power design - power on/off sequence - PLL design guide - power consumption data
dfefe.doc
- 该高频正弦信号发生器基于直接数字频率合成（DDS）和数字锁相环技术（DPLL），以微控制器（MCU）和现场可编程逻辑门阵列（FPGA）为核心，辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数（A/D）－数模（D/A）转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a
Deltaementation
- Delta_Sigma调制 锁相频率合成器的设计与实现-Delta_Sigma modulation PLL Frequency Synthesizer Design and Implementation
10.1.1.19.9992
- complete project design for pll and dds
38504873-pll
- Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
pll_module
- 基于verilog的 FPGA内部PLL模块设计-Based on verilog FPGA PLL design internal modules
test_sdram
- 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block,
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
PLL
- PLL锁相环的详细介绍，电子书包括设计及应用，对研究锁相环的很有用-Introduction of PLL，include design and application，it s useful for research of PLL
jtcurran_oscpll_taes2012
- Digital GNSS PLL Design Conditioned on Thermal and Oscillator Phase Noise