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Des2Sim
- 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程,作为我这一段 时间自学 FPGA/CPLD 的总结,如果有什么不正确的地方,敬请各位不幸看到这篇文章的 大侠们指正,在此表示感谢。当然,这是一个非常简单的时序逻辑电路实例,主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1; Altera 公司出品的 Quartus II 4.2;Mentor Graphics 公司出品的 ModelSim
AND_TOP
- Simple 7 segment up-counter for Quartus II 4.
SPL_TOP
- 7 segment up-counter for Quartus II 4.
tutorial
- quartus ii 6.0版本tutorial文件,在不同的版本中会出现不同的说明介绍,包括6.0/ 7.2/ 8.0。-tutorial for quartus ii 6.0 that illustrate a quiker way to get access of basic feature of the design software
bujindianjikongzhi
- 在quartus II下用verilog编写的步进电机位置控制程序,其中包含7个子模块和1个顶层模块,本程序层次清晰、功能明确。乃个人收藏,推荐大家下载学习!-Verilog in quartus II, prepared under the stepper motor with position control program, which contains seven sub-modules, and a top-level module, the program-level clarity
PipelineCPU
- Quartus II 7.2环境中,采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序,实现190.7分频,可以将50MHz时钟频率分频成约等于2^21Hz频率,方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
altera_de2_vhdl
- Tutorial of VHDL with Altera DE2 board: quartus II and DE2 board The target do the BCD sum of input data coded with the switches and display the result on 7 segment display
VEDA7LED
- 采用QUARTUS II 7.2 (32-BIT)工具实现的两位7段数码管动态扫描显示的VHDL程序。硬件电路采用8位拨位开关控制,高四位控制左数码管,第四位控制右数码管。芯片采用EP1C6T144FPGA器件。-By QUARTUS II 7.2 (32-BIT) tools to achieve the two 7-segment digital tube dynamic scan showed the VHDL program. 8-bit hardware with dial-bit s
0710200134
- 本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想,大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用,有着非常现实的意义。-This paper describes a multi-clock design. The program has the time, the whole point of time, school ho
7.5.0
- 利用汇编语言,QUARTUS ii软件编写的模拟CPU工作原理的一个程序。主要功能有寄存器,存储器,总线的工作方式的模拟-The use of assembly language, QUARTUS ii software development, simulation of a CPU works program. Main function registers, memory, bus simulation work
Chapter-7
- 练习七在verilog hdl中使用任务(task)319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
Crack_QII72_FULL_License.RAR
- Quartus II 7.2最完美的license破解器!-Quartus II 7.2 FULL and perfect License!
fenpin
- 开发工具是quartus II 7.0以上版本,这是一个verilog语言的分频器设计,个人作业设计,供参考学习-verilog,quartus II 7.0
RS232
- RS232与FPGA的通信程序,经过QUARTUS II 7.1的测试,结果正确-RS232 communication program and FPGA, QUARTUS II 7.1 test results, correct
clock
- 用vhdl写的数字电子时钟,能够定闹钟,定点报时,调时,用Quartus II 7.2 (32-Bit)写的,压缩文件,里面有源程序,仿真文件等(就是所建的工程)-Digital electronic clock vhdl write, to set the alarm clock, designated chime tune, written using Quartus II 7.2 (32-Bit), compressed files, source code and simulation
clock
- 数字时钟 LCD1602显示 可以校时。 编译环境QUARTUS II 7.2 -Digital clock LCD1602 display can be corrected. Compilation environment QUARTUS II 7.2
LCD1602-DRIVER(vhdl)
- LCD602的驱动器模块源代码 可直接使用 编译环境QUARTUS II 7.2-LCD602 drive module source code Can be used directly Compilation environment QUARTUS II 7.2
DE2_i2sound
- Altera DE2开发板例程源码,原版的为基于quartus II 7.2开发的,在9.0以上的版本上编译通不过,本源码为基于quartus II 9.0以上版本-Source code of Altera DE2 development board
Quartus-7.2-32-Bit-Crack-Bundle
- License generators and license.dat to quartus II ALtera