搜索资源列表
logicassign
- 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd-The same base type to distinguish the two types of assignment compatibility issues, the various sources described in the order of the compiler: logic.vhd, assign.vhd
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
gcd_disp
- 最大公约数七段显示器编码,各个源描述的编译顺序gcd_disp.vhd,vhdl.vhd,stim.vhd-Seven-Segment Display common denominator coding, various sources described in order to compile gcd_disp.vhd, vhdl.vhd, stim.vhd
TLC
- 交通灯控制器编码，源描述的编译顺序tlc.vhd，est_vector.vhd-Traffic lights controller code, the source described in order to compile tlc.vhd, est_vector.vhd
conditioner
- 空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd-Air-conditioning systems finite state automata encoding, various sources described in order to compile conditioner.vhd, conditioner_stim.vhd
61EDA_D1077
- 数字钟电路原理图程序清单 ********顶层程序描述*********** 程序：TIMER_SET.VHD-Digital clock circuit schematic process procedures described in the top of the list of******************* procedures: TIMER_SET.VHD
polar2rect_VHDL
- 是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd-Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cord
wave_produce_VHDL
- --文件名：mine4.vhd。 --功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节
frequence_VHDL
- 采用等精度测频原理的频率计的程序与仿真 --文件名：PLJ.vhd。 --功能：4位显示的等精度频率计。 -Such as the accuracy of frequency measurement using the principle of the frequency of the procedure and simulation- the file name: PLJ.vhd.- Function: 4 shows, such as precision frequency me
SYNTHPIC.ZIP
- The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the licen
JIAOTONGDENG
- 本程序(jtd.vhd)是十字路口交通等的主程序,其是顶层电路模块。-This procedure (jtd.vhd) are at the crossroads of the main transportation, it is the top-level circuit module.
stereo_vision
- Stereo-Vision circuit descr iption, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical an
VHD_QCOW
- CRITRIX 提供有关QCOW 及最新支持VHD虚拟磁盘文件操作源码-critrix qcow and vhd
vh2sc
- 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and boole
test
- Verilog test file not vhd-Verilog test file not vhd
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
usb_blaster
- 文件列表(日期：2005080604~2009101613)
8080cpu
- this code for cpu 8080 design -this is code for cpu 8080 design
dingshi
- quarters2编写的定时器.vhd为源程序-prepared quarters2 timer. vhd for source
clk_div.vhd
- 实现对时钟信号的技术分频，程序简单易懂，对于初学VHDL者来说，提供了一个良好的方法。-Implementation of the clock signal frequency technology, the program easy to understand, for the beginner who VHDL, provides a good approach.