搜索资源列表
dec.vhd
- vhdl code for a 16 bit decoder design
FIFO
- 512×8bid的FIFO 含工程文件,基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
ADC0809VHDL
- 文件名:ADC0809.vhd功能:基于VHDL语言,实现对ADC0809简单控制说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟号,这里由FPGA的系统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt
H.264
- H.264标准解码器全部verilog源码,包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
fenpinqi
- 此文件为EDA的8位分频器,但可以用于不同位分频器,如:1位到10位等,用Quartus软件来,以文件VHD格式编译即可-This document is for EDA 8-bit prescaler, the prescaler can be used in different places, such as: 1-10 and so on, using Quartus software to VHD format file can be compiled
Xilinx USB JTAG 下載端程式
- Xilinx USB JTAG 下載端程式 -The jtag_logic.vhd in this directory describes the logic for a parallel-serial converter to be connected to a FT245BM USB chip from FTDI Inc
ad7823.vhd
- ad7823的VHDL驱动程序,测试在quartus9.0下编译通过-ad7823 driver of VHDL, the compiler under test through quartus9.0
contador
- Contador hexadecimal para UP1 (.vhd)
03.EDK8.2
- 使用xilinx virtex4芯片,设计环境为EDK,其中包含uart,片外sram操作,flash操作,DDR SDRAM操作,MAC自发自收,audio,video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
ROM_by_Matlab
- Rom.vhd with Matlab and file hex
baheyouxiji
- 用vhdl写的拔河游戏机代码,后缀名改为vhd即可-the code of baheyouxiji in vhdl
11
- 交通灯的描述,主要是用了VHD的语言来编写的-light
arp3
- it s an audio project
YEAR_COUNT.vhd
- 电子数字日历中的年代码 ,可以记到万年,俗称万年历-Electronic digital calendar year code, can be credited to years, commonly known as calendar
qiangdaqi
- (1) 抢答器线路测试功能 为了保证比赛的正常进行,比赛前需要调试线路能否正常工作。 (2) 第一抢答信号的鉴别和锁存功能 可以判断谁最先抢到回答的资格,其相应的绿灯表示抢答成功,并具有锁存功能,一直到下一题开始。 (3) 犯规警示功能 可以判断出参赛者有没有在主持人读题的期间按下抢答器,有则相应的红灯亮,同时取消其本轮抢答资格。 (4) 计时功能 可以预置时间,可以进行倒计时并且将时间显示出来。 (5) 计分功能
stack.vhd
- stack for the protocol used to implement into FPGA
xapp860
- 16通道DDR的LVDS接口(VHDL,Verilog and doc)-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
can_parts
- This the CAN bus controller for implementation inside any FPGA-This is the CAN bus controller for implementation inside any FPGA
hpiir
- FPGA文件程序,irr型低通滤波器,vhd程序 -FPGA program file, irr-type low-pass filter, vhd procedures
DAC0832
- 8.6 DAC0832 接口电路程序 见随书所附光盘中文件:DAC0832VHDL程序与仿真。 --文件名:DAC0832.VHD --功能:产生频率为762.9Hz的锯齿波。 --最后修改日期:2004.3.18。 -8.6 DAC0832 Interface Circuit procedures, see the book with accompanying CD-ROM in the file: DAC0832VHDL and simulation procedures