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MyUART
- 经过我严格测试，已经获得实际应用的RS232串口通讯的VHDL编写的程序，对于初学者绝对有帮助！-After I tested, has received the application of the RS232 serial communication program written in VHDL, for absolute beginners help!
LCD12864_TEST
- VHDL语言，１２８６４显示屏的驱动程序，本人已在自己开发板上测试成功，需要的朋友下载后根据自己的开发板稍加修改即可-VHDL, 12864 display driver, I have tested successfully in my own test board, you need slightly modified according to your own test board
Marquee
- VHDL语言设计的跑马灯程序，使用8段数码管，并能递减计时，计时时间到蜂鸣器响声输出，数据在数码管上滚动显示，在试验箱上测试通过。-Marquee VHDL language design process, with 8 of the digital control, and can decrease time, time time to sound the buzzer output, data on the digital scroll in the chamber on the test.
UART
- 串口VHDL程序，Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.
spi
- 描述了总线的vhdl程序，并且有测试语句的描写 仿真之后可以实现-Describes the bus vhdl program, and a test statement, after describing the simulation can be achieved
sdfa
- LCD控制VHDL程序与仿真, 各位可以试一试,我已完成仿真和测试-LCD control procedures and VHDL simulation, you can try
UART_MODULE
- 本程序是一个简单的232串口程序，采用VHDL语言编写，并已在3S500E上测试通过-This program is a simple 232 procedures, the use of VHDL language, and has been tested on the 3S500E
test1602
- 1602的VHDL程序！在自己的板子上一测试测试成功！-1602 VHDL program! In their board a test success!
sram_vhdl
- 基于vhdl的sram读写访问程序，经过前后仿真及板上实际测试-failed to translate
UART
- 异步串口收发程序，波特率4800。VHDL写成。在ALTERA开发板上测试成功。-This is a UART program, with a fixed 4800bps. Tested successfully on an Altera divice.
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
fpga_uarst
- fpga USART通信，VHDL语言编写，通过测试。程序全面运用了状态机编程-The fpga the USARTs communications, VHDL language, pass the test. The entire process of the use of state machine programming
lcd1
- vhdl写的fpga控制12864液晶程序，经测试可用-vhdl write the fpga control 12864 procedures, the test can be used
VVHDL_32bit_tH
- VHDL写的32位计数，两个四位共阳数码管输出串口输出+数码码管显示的计时器程序每次停止后串口输出。，已通过测试。 -VHDL written 32 count, two four sun digital serial output tube output serial output the+ digital code to display the timer program each stop. , Has been tested.
4_1mux
- 通过Vhdl语言实现 2—1 mux 并基于 2-1 mux 完成4-1 mux 程序和test bench的编写，测试成功 -2-1 mux realized through Vhdl language based on the 2-1 mux 4-1 mux of procedures and test bench preparation, the test is successful
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
sdramtest
- vhdl语言编写读写三星SDRAM程序，包含读写控制程序，地址转化程序，测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
Xilinx_vga_games_design
- 经典的程序，用VHDL编写的游戏，俄罗斯方块，在赛灵思Spartan板子上测试成功-Classic procedures, written in VHDL game, Tetris, on the board of the Xilinx Spartan test
test12
- 自己用VerilogHDL语言编写的时钟程序，包括时钟进位计数模块，数码管显示模块和闹钟模块。在cpld芯片上经测试有效（开发环境没找到VerilogHDL，就选了VHDL，其实他们不一样的……）-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te