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VHDL_clock
- VHDL数字钟设计程序 设计要求 基本要求: 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响);--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (
clock
- 多功能数字钟,VHDL语言编写;是EDA学习中常见问题-CLOCK
DigitalClock
- 该数字钟,采用VHDL语言编写,具有即时,跑表,调时,调分,闹铃等功能,另外还可以增加一些功能,例如正点报时等-The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
project
- 介绍了利用VHDL硬件描述语言设计的简易数字钟的思路和技巧。在QuatusⅡ开发环境中编译和仿真了所设计的程序,并在可编程逻辑器件上下载验证。仿真和验证结果表明,该设计方法切实可行,具有一定的借鉴性。-digital clock
digital_clock1
- 多功能数字钟 vhdl 具有报时功能-digital clock
Written_in_VHDL_Digital_Clock_Design
- VHDL语言编写的数字钟设计Digital Clock Design,电子系很经典的实验设计-Written in VHDL, Digital Clock Design Digital Clock Design, Department of Electronic Engineering is the classic experimental design
shuzizhong
- 基于VHDL的数字钟的设计,本文给出了详细的代码,直接可用!-VHDL-based digital clock design, this paper presents a detailed code, directly available!
clock
- 数字钟,用VHDL 编写。具有计时,校时(调分调时),报时功能-Digital clock, written with VHDL. With time, school time (when the tone on tones), timekeeping function
final
- 基于VHDL的数字钟实现,适用于大学数字电路与逻辑设计课程的期末考试或实验内容-VHDL-based digital clock implementation
shuzizhong_VHDL
- 用VHDL语言写了数字钟程序,并用数码管显示,经过硬件调试可行-timer clock
VHDLDigitalClock
- 数字钟的VHDL语言实现基本功能,包括 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响); -Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1
SHUZIZHONG
- 基于VHDL语言的数字钟的,包括显示,按键控制等-无
DigitalClockBasedonVHDL
- 基于VHDL编写的数字钟,可以设置时间、闹钟,实现报时等功能。-Written in VHDL-based digital clock, can set time, alarm clock, to achieve timekeeping functions.
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
mclock
- 用VHDL编写的带闹钟报时功能的数字钟 ,现代数字系统设计作业。 采用文本图形混合输入,在maxplus2 10.0运行通过-Written by VHDL figures with alarm chime clock, modern digital system design work. Graphics mixed with text input, run by the maxplus2 10.0
fpgaclock
- 数字钟小程序,FPGA程序,用VHDL编写的源程序-failed to translate
shuzizhong
- 基于VHDL的数字钟,可以整点报时和校准时间-VHDL CPLD
clock
- vhdl 简易数字钟 基于fpga 使用quartus7.0,便于移植到其他平台
watch
- 本文件为电子设计而开发的多功能数字钟VHDL语言完整源代码 --该数字钟实现的功能有时间,秒表,闹钟,年月日的显示设置等 -This document is multi-functional electronic design and development of a complete VHDL, digital clock source code- the digital clock function can be achieved time, stopwatch, alarm clo
music1
- VHDL 多功能数字钟源码音乐模块2,自扒简谱-Multi-function digital clock source VHDL music module 2, since the expense of musical notation