搜索资源列表
Verilog_divid
- vhdl语言描述传统除法器,传统乘法器的改进,从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
chufa
- 用VHDL设计的四位除法器,可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
BCD_divid_new
- VHDL语言编写的8位BCD除法器,可以实现浮点数计算,只支持正数运算,并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
lab4_5
- 用VHDL实现串行除法器,16位被除数,8位除数-Using VHDL serial divider, 16 dividend, divisor 8
chufaqi
- 用vhdl编写的N位除法器,适合初学者学习和编程- written in VHDL a N divider, suitable for beginners to learn and program
divider
- 主要是基于VHDL的五位除法器设计,基于eda试验箱的设计。-Five main divider VHDL-based design, based eda chamber design.
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
DIVIDER
- 大家好,我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ,商M位,余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程,直接测试。鄙人测试都是无错误的。愿尊驾下载后,积极评价,以便于相互交流,学习。O(∩_∩)O谢谢.2015年5月7日于芬兰,图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
my_32fp_mult
- 这是一个计算32位浮点数的除法器,ALTERA的FPGA可直接用,用VHDL语言写的,希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
multiplieranddivider
- 乘法器和除法器的VHDL实现方法,可运行,占用逻辑资源少。-VHDL descritpion about muiltiplier and divider
AnJian_1602
- 计算器设计。采用了现场可编程逻辑器件FPGA设计,并基于VHDL语言实现加减乘除功能,并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形,并下载到试验箱,用实验箱上的按键开关模拟输入,用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能,其结果简单,易于实现。-Calculator design. Using a field programmable logic d