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uart
- UART vhdl code,recive data from uart port on fpga board
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
uart-VHDL
- uart-VHDL 带奇偶校验位 比特率为1152-uart-VHDL add parity check bit rate is 115200
uart
- QUARTUSII 环境 内容为整个工程 ，可以直接用 VHDL 实现UART通讯-QUARTUSII environmental elements for the entire project, you can directly communicate with the VHDL implementation of UART
vhdl
- 基于PicoBlaze的实时时钟设计。PicoBlaze是Xilinx的8位软核。采用汇编语言编写。-Uart real timer
uart-user-guid
- uart 使用指南，以及协议介绍，对verilog vhdl编程大有裨益-uart user guid
rs232
- the vhdl driver:uart communication:rs232(EIA):baud:9600kbps
UART
- 异步串口收发程序，波特率4800。VHDL写成。在ALTERA开发板上测试成功。-This is a UART program, with a fixed 4800bps. Tested successfully on an Altera divice.
uart_lcd1602
- 点亮altera公司DE2代开发板的1602液晶，采用niosII方法。-Light the LCD1602 of the altera DE2 board with the niosII method
uart
- verilog VHDL实现的DE2 uart-Verilog VHDL the uart of the DE2
altera-uart
- ALTERA UART sopc 软核的VHDL描述-ALTERA UART VHDL DESCRIBE
UART
- IM DESINING VHDL COD EIN IS THIS CODE IS GOD AND TESTIN VERY GOOD
uart
- uart的vhdl源码，实现fpga的通用串行异步收发接口的设计-the uart the vhdl source to achieve fpga universal serial asynchronous transceiver interface design
uart
- 用VHDL实现UART通讯（暂时只能发送）-UART communication using VHDL (temporarily only send)
uart-vhdl
- 不错的uart总线程序，已经测试过，没有问题啊-Good uart bus program, has been tested, there is no problem ah
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
uart
- uart串口通讯，波特率任意可调，采用vhdl语言编写，ise和quartus均可使用-uart serial communication baud rate of any adjustable
VHDL
- 自己写的串口程序，其中接收模块和发送模块分开了，主要对用状态机编写串口协议!-UART TXD，RXD
UART-VHDL-QUARTUS
- uart vhdl quartus for altera