搜索资源列表
test_state
- VHDL code for UART transmission & reception.
uart_tx
- UART EDGE TRIGGERED ONE SHOT VHDL
a_vhd_16550_uart_latest.tar
- 16550 uart vhdl source code
uart_proj
- uart serial vhdl, sender and transmitter for full speed 115200 bods
uartvhdl
- 该程序是基于UART的控制，有VHDL和verilog的源码，共有兴趣的朋友参考-The program is based on the UART' s control, there is VHDL and verilog source code, a total interest of a friend reference
example
- 我FPGA开发板的程序！！！包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了，主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..
UART_prj_ViHDL
- vhdl project at sbu uni in iran uart
UART_VHDL
- UART VHDL component
uart_core(V2_0)
- 本例为自己编好的VHDL的基于uart的FPGA的 设计。-In this case for their own good VHDL code uart of FPGA-based design.
uart16750_latest.tar
- UART 16750 VHDL core
muart_latest.tar
- vhdl minimal uart core
VHDL_Complex_Examples
- Some slides with complex vhdl examples. There you can find UART,ROMs,RAMs and other source codes and details for every one
UART_VHDL
- 特别适用于TI C6000 DSP扩展UART的VHDL源代码。-a VHDL source code specially for TI C6000 DSP to extend UART
UARTofVHDL
- 基于vhdl的uart程序设计：完全按照论文格式编写。-The uart vhdl-based Programming: paper format exactly as written。
SEND422
- 这是用VHDL编写的代码，是RS422在UART协议层上实现数据发送的过程，很有用的啊！-It is written in VHDL code, is RS422 UART protocol layer in the data transmission process, useful, ah!
mmuart_latest.tar
- simple UART code written in vhdl test included
uart_vhdl_verilog
- 串口FPGA的实现源码，VHDL和Verlog两种语言源代码。-UART FPGA implementation source code, VHDL and Verlog two languages source code .
UART2
- 基于SPARTAN-3E的与计算机的异步串行通信，可根据需要更改波特率等等。-SPARTAN-3E based on the asynchronous serial communication with the computer, according to the need to change the baud rate and so on.
rs232
- VHDL 语言如何写串口的源代码，很详细的-VHDL for uart
UARTModule
- Uart的VHDL实现，用ISE12.1建的项目。-Uart usingVHDL to implement