搜索资源列表
video_compression_systems
- 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio / video codec
JPEG2000
- jpeg 2000 encoder complete document
JPEG2000
- JPEG 2000 国际标准系列 ISO/IEC FCD15444-1~6-JPEG 2000 international standard series ISO/IEC FCD15444-1 ~ 6
jpeg2000_intel
- Intel® Integrated Performance Primitives JPEG 2000 Sample for Windows*-Intel ? Integrated Performance PrimitivesJPEG 2000 Sample for Windows*
63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
jpeg
- jpeg图像处理 用verilog语言处理的源代码-jpeg
JPEG_Encode_verilog
- JPEG Encoder，JEPEG编码的Verilog代码-JPEG Encoder, JEPEG coded Verilog code
Jpeg_decoder
- It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
jpeg_mpeg_264_src
- 最完整的jpeg/mpeg4/h.264 verilog hdl 源码集合-The most complete collection of jpeg/mpeg4/h.264 verilog hdl source
JPEG
- 用Verilog描写应用于数字图像压缩系统--JPEG有测试文档-With Verilog descr iption of the system used in digital image compression- JPEG with test documentation
fpga-jpeg
- JPEG硬件解码器设计 verilog实现-JPEG hardware decoder design verilog implementation
jpeg-codec-in-verilog-HDL
- jpeg codec in Verilog HDL.-jpeg Code decoding used by Verilog HDL。
verilog
- JPEG CODEC Decode and encode
fpga-jpeg
- jpeg编码verilo语言的FPGA实现-jpeg encode fpga implement with verilog
verilog
- jpeg源码，图像编码的硬件描述语言设计,可用作硬件加速处理参考-jpeg source, image coding hardware descr iption language design
JPEG-Encoder
- JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
fpga-jpeg
- 包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
JPEG
- JPEG Encoder Verilog Source Code