搜索资源列表
DP8051_FREE
- Free 8051 core upload
oc8051_verilog
- 兼容8051的内核oc8051,verilog版本的-8051-compatible core oc8051, verilog version of
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
Revised_Verilog_code
- 简弘伦:Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
mc8051_design
- 8051内核的设计,用Verilog硬件描述语言实现,在modelsim环境下进行仿真。-8051-core design, using Verilog hardware descr iption language, in the modelsim simulation environment.
AES
- AES算法的verilog代码,即AES算法IP核-ip core for AES
i2c
- 基于FPGA的I2C内核的verilog程序-Verilog program of I2C core base on FPGA.
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
i2c_master_slave_core
- I2C master/slave IP core
yavga
- This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable chars
tripledes
- 3-DES加密IP核VHDL源码,3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频(DDC)系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
aes_core
- aes_core verified verilog ip core-aes_core verified verilog ip core
arm7
- ARM7core verilog 源代码-ARM7 core verilog source code
qam_64
- 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
8051Verilog
- 利用FPGA可编程的特点,在内部编写了一个8051单片机软核。已通过调试。-The use of FPGA programmable features, in-house preparation of a 8051 soft-core. Passed debugging.
Ipcoredesign
- 微电子/软硬IP核设计:IP核脚本指南,模型开发指南-Microelectronics/soft and hard IP core design: IP core scr ipting Guide, Model Development Guide
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
arm7verilog
- ARM 7 免费ip 核, verilog语言描述-arm7 free ip core, verilig DHL