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grlib-tmtc-1.0.18.tar
- Zipped LEON3 processor VHDL core.
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
pipelined_fft_64
- 利用IP Core编写的Verilog程序，实现FFT变换，希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
8051vlog
- 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
CoreCFI
- VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
8088verilog
- intel8088的verilog core ，完整的RTL-intel 8088 verilog core， all RTL
Q8051
- A 1T51 core which contain 16 verilog files. this mcu core consiste with standard 51
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
DW8051_core
- 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
61EDA_C1910
- ARM9架构简单CORE实现，可以综合，有实现步骤和说明，Verilog代码编写-ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
fft_2011_3_23(COMPLETE-FFT1024)
- VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE
UDP_Core
- 本人用verilog编写的UDP协议，经测试可用。-I am prepared to use verilog UDP protocol, the test is available.
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
dds
- 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib