搜索资源列表
aes-core-include-testbentch
- aes core的verilog代码，包含测试代码和波形文件-aes core verilog code including testbentch
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
jesd204
- xilinx平台 jesd204核例化使用示例(Xilinx platform jesd204 core example of the use demo)
tdc-core-master
- TDC的HDL实现代码，在SPARTAN6平台上验证过。(The HDL implementation of TDC function, verified in spartan 6 platform.)
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
hdl-2014_r2.tar
- AD9361 IP 核，Linux版本，Vivado2014.2(AD9361 IP core, used on Linux, Vivado2014.2.)
hdl-2014_r2
- AD9361 IP核，Windows版本，Vivado2014.2(AD9361 IP core, used on Windows, Vivado2014.2)
hdl-2015_r2.tar
- AD9361 IP核，Linux版本，Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2015_r2
- AD9361 IP核，Windows版本，Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
hdl-2016_r2.tar
- AD9361 IP核，Linux版本，Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2016_r2
- AD9361 IP核，Windows版本，Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
8051-master
- 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU inte
Beautiful Restful API in ASP.Net Core
- restfull api for the team to beryfy what is the p[robme
avalon-i2c
- 基于verilog的I2C实现，可以通过软核或者ARM核进行控制哦。(The implementation of I2C based on Verilog can be controlled by soft core or ARM core)
FFT v1
- IP core fft verilog code example
06_pll_test
- 锁相环IP核的使用，包括详细的配置，适合学习使用；(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
10_rom_test
- rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
MIPS-Verilog-master
- MIPS R3000 microprocessor core
parallel_norflash_test
- ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)