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taxiwork
- 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠，应用于实际当中有较好的实用价值和较高的可行性
01_GettingStarted
- This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken fro
v2html.tar
- v2html - verilog to html converter 主要为FPGA和ASIC工作人员
Pcit32vhdl
- PCI 32 target IP for Fpga/asic Designer
pci_express_crc
- PCI express CRC rtl core for Fpga/asic Designer
mit-ofdm-wifi
- MIT关于OFDM收发器、WIFI收发器的ASIC和 FPGA硬件开发源码及资料，比较不错的资料OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for 802.15 (WUSB) is currently being worked on. 802
FPGAdesignguide
- 华为FPGA设计流程指南:本部门所承担的FPGA设计任务主要是两方面的作用：系统的原型实现和ASIC的原型验证。编写本流程的目的是：在于规范整个设计流程，实现开发的合理性、一致性、高效性。形成风格良好和完整的文档。实现在FPGA不同厂家之间以及从FPGA到ASIC的顺利移植。便于新员工快速掌握本部门FPGA的设计流程。
DSP-External-Memory-Interface-Module
- EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chi
ASIC-and-FPGA-Verification---A-Guide-To-Component
- ASIC and FPGA Verification - A Guide To Component Modeling
HUAWEI-FPGA-design-procedure-guide
- 本部门所承担的FPGA设计任务主要是两方面的作用：系统的原型实现和ASIC的原型验证。编写本流程的目的是： 在于规范整个设计流程，实现开发的合理性、一致性、高效性。 形成风格良好和完整的文档。 实现在FPGA不同厂家之间以及从FPGA到ASIC的顺利移植。 便于新员工快速掌握本部门FPGA的设计流程 -HUAWEI FPGA design procedure guide
FPGA
- FPGA开发全攻略_工程师创新设计宝典.FPGA 是英文 Field Programmable Gate Array 的缩写，即现场可编程门阵列，它是在 PAL、GAL、CPLD 等可编程器件的基础上进一步发展的产物。它是作为专用集成电路(ASIC)领域中的一种半定制电路而出现的， 既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。它是当今数字系统设计的主要硬件 平台，其主要特点就是完全由用户通过软件进行配置和编程，从而完成某种特定的功能，且可以反复擦写。在 修改
Final
- A "Tank Duel" game based on FPG, developmented in VHDL. -- Final Project in ASIC & FPGA Design class -A "Tank Duel" game based on FPG, developmented in VHDL.-- Final Project in ASIC & FPGA Design class
Lab3
- A Combinationa Divider Design in VHDL -- homework in ASIC & FPGA Design cla-A Combinationa Divider Design in VHDL-- homework in ASIC & FPGA Design class
Lab3B
- A Sequential Divider Design in VHDL -- homework in ASIC & FPGA Design cla-A Sequential Divider Design in VHDL-- homework in ASIC & FPGA Design class
asic
- fpga在电路设计的规则，宝贵的经验，不容错过。-fpga circuit design rules, valuable experience not to be missed.
Synthesis-of-Arithmetic-Circuits-FPGA--ASIC-and-E
- Digital signal processing - Application to FPGA
UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n
- UART code using VHDL for FPGA or ASIC
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
LBG64_double_CLK
- 数据压缩算法的硬件实现ASIC&FPGA（矢量量化算法）-Data compression algorithm implemented in hardware ASIC & FPGA (vector quantization algorithm)
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)