搜索资源列表
ASK
- 出租车自动计价器设计,用于学习VHDL编程实现,FPGA的基本设计方案
ask调制解调 vhdl 仿真
- ask调制与解调的vhdl仿真
FPGAVHDLd
- 多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LC
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
singnal
- VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
dds_9760_ALL1
- DDS频率精确步进100HZ，拔码选择FSK，PSK，FM，ASK功能。-dds base on vhdl
dds_9760_OK
- ＤＤＳ信号源程序，用ＶＨＤＬ编的。里面可用拨码开关选择相应的功能：ＦＭ，ＡＳＫ，ＰＳＫ，ＡＭ（这一点实现的不是很好），但其它的很好。频率可达２５Ｍ-DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequen
module_dem
- 用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现-Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation
ask_fsk
- 数字通信系统振幅键控ASK信号和频移键控FSK的调制与解调的VHDL代码-ASK amplitude shift keying digital communication system signal and the frequency shift keying modulation and demodulation of the VHDL code for
ddsmodem
- modem ask, fsk, psk program susing DDS
100503
- FPGA有价值的27个编程例子。包括LED控制，LCD控制，ASK调制与解调，DAC0832接口电路程序-27 example about FPGA
FPGA_verilog
- FPGA很有价值的27实例:如ASK、PSK、FSK调制与解调VHDL程序及仿真等-FPGA verilog
tiaozhi
- 使用vhdl完成了ask psk fsk的调制和解调-Completed using vhdl ask psk fsk modulation and demodulation
VHDLprogram
- 有ASK,MSK,PSK,MASK,MFSK的VHDL程序实现及仿真结果分析。-There ASK, MSK, PSK, MASK, MFSK the VHDL program implementation and simulation results.
example_VHDL
- VHDL 语言的初级实例，27个。电子钟，mask，ask-VHDL, the primary instance, 27. Electronic clock, mask, ask ... ...
DDS
- DDS 用VHDL写的输出的正弦波程序 调频 调幅 调相-DDS WRITE IN VHDL ,including FSK ASK
fpga
- 基于FPGA的信号调制，可产生正弦波，并进行ASK调制和AM调制-FPGA-based signal modulation, can produce sine wave, and the ASK modulation and AM modulation
code
- <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
ASK
- 基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-VHDL hardware descr iption language based on the ASK baseband amplitude modulation signal
8.9-ASK-debug-VHDL-program
- 基于VHDL硬件描述语言，对基带信号进行ASK调制-VHDL hardware descr iption language based on ASK modulation baseband signal