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game
- 小游戏规则： led(0 to 3)是按一定规律不断发亮，每次只有一个灯亮，每个灯都和我们BASYS板上的四个按钮中的一个对应着， 当Led(0 to 3)中的灯亮时，我们要按对相应的按钮时候，在led(4 to 7)中对应的按钮就会亮起， 并且八段码显示的数字也相应的加上一，要是按错了led（4 to 7）灯不亮，且显示数字减1。-The rules of the game: led (0 to 3) is according to certain rules constant
Control_Display
- Controlador de display siete segmentos en verilog El archivo contiene selector decodificador multiplexor y archivo para simulacion Sevent segment dispay controler in verilog for basys nexys2 nexys3 fpga boards This file have a decoder, selector
UniversalDIV
- UNIVERSAL FREQUENCY DIVIDER pin sets for Digilent Basys 2 (Spartan3E-250) fout = (K(0)*100+ K(1)*10 + K(2))*10K(3)
pingball
- 用verilog写得弹珠小游戏，在BASYS平台上运行的-Pinball game with verilog written, running on a platform in BASYS
wave-generator-and-VGA-on-basys2
- 基于BASYS开发板的波形发生器和示波器设计，共有三角波方波锯齿波以及正弦波，最后VGA在显示屏中显示波形。-Waveform generator and oscilloscope design BASYS development board based on a total of sawtooth and square wave triangle wave sine wave finally VGA display in the display.
Twobits-Adder
- Two bits Adder, this code allows add two bits variables using switches of FPGA, the result is shown in seven segments display. Include seven segments decoder module. The program was verified using BASYS 2 FPGA.
Frecuency-Divisor
- This code Use the 50 Mhz clock of BASYS 2 FPGA to generate a frecuency divisor (choose the div value using FPGA Switches). The result is shown in two leds to compare, one have a frecency fixed (with out div ) and the secon led showm the div selected
basys3_basic_demo
- Basys 3 开发板的自带程序，包括LED 数码管 按键 鼠标等各项功能的演示。-Basys 3 development board comes with the program, including the LED digital control buttons and other functions of the mouse.
Display_7seg
- Basys 3 开发板入门实验，按键控制7段数码管显示试验。-Basys 3 development board entry test, key control of the 7 section of the digital tube display test.
Oscilloscope
- Basys 3 示波器工程源代码，可以参考。-Basys 3 oscilloscope source code, can refer to.
Piano_vhdl
- Here is the Piano code for FPGA(Basys 2) with switches.
rna
- top transmition of implement spi, compiled in vivado 2016 in basys 3
project_fir_test
- 基于verilog的FIR滤波器设计，使用BASYS３作为开发工具-Verilog based FIR filter design, the use of BASYS3 as a development tool
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
计时器设计
- 简单的计时器设置，可在实验板上完成分钟和秒的计数(Simple timer settings, can be completed on the experimental board minutes and seconds count)
模60计数器
- 基于basys2的模60计数器设计，语言verilog(Design of module 60 counter based on basys2, Language Verilog)
Basys-3-GPIO-2016.4-1
- Test for GPIO for basys3, made by digilent
Basys-3-Keyboard-2016.4-1
- Demo for keyboard, basys3 made by digilent