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ContadorBCD
- Verilog counter 0000 to 9999 with BCD visualization
BCDadd8
- 8位的BCD加法器,BCD表示即4bit表示一个十进制数,取值范围是0000-0110,verilog代码实现-8-bit BCD adder, BCD said that 4bit represents a decimal number, range is 0000-0110, verilog code
4BCDcodeaddition
- 用verilog实现两个4位BCD码数字的十进制加法计算-4 bit BCD coded decimal addition calculations
counterms
- verilog语言写的可置数的倒计时计数器,共四位bcd码,分别为分钟两位和秒两位。波形完美无毛刺.开发环境没找到verilog只好写了vhdl-verilog based counter for minutes and seconds
counter
- This is 2-BCD numbers Counter on board Altera DE2 Code Verilog HDL (You must import DE2_pin_assignments.csv to use this code)
Lab2_Part1
- display BCD code(0-9) using 7-segment displays in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
Lab2_Part2
- converts a 4-bit binary code to 2-digital BCD code in verilog code. Implements on educational kit Altera MAX7000s EPM7128SLC84-7.
bin2bcd.v
- FPGA Verilog BIN 2 BCD Conversion code.
bit7_Binary_to_BCD_LED
- 二进制转十进制BCD码 Verilog语言 quartus-Binary to decimal BCD code Verilog language quartusII
Binary_to_BCD_Converter
- This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
binary2bcd
- binary to bcd code converter design using verilog
verilog-code-FOR-COMPARATOR--TFF-AND-BCD-TO-7SSD.
- // File : 4 Bit Comparator design using behavior modeling style.v-// File : 4 Bit Comparator design using behavior modeling style.v
t1_bin2bcd
- 二进制转BCD的verilog程序,实现二进制数到BCD的转换,该程序具有节约FPGA的内部逻辑资源等特点- Binary to BCD s verilog procedures to achieve binary number to BCD conversion, the program has an inter
bcdadd
- 4-Bit BCD Adder in Verilog
bcdsubtract
- 4-Bit BCD subtract in Verilog
Lab8_binbcd4
- 4位二进制-BCD码转换器的设计与实现.4位二进制-BCD码转换器的真值表,本实验中用Verilog语句来描述。-Design of 4 bit-BCD converter and implementation of.4 binary-BCD code converter truth table, use the Verilog statement in this experiment to describe.
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计,涵盖原理图设计、文本设计以及进行波形仿真,并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
bcdflag
- verilog code bcd adder using flag register
BCDcoder
- 关于三位数的BCD转二进制,和二进制转BCD码。用verilog编写-BCD to Binary and Binary to BCD
bcd_adder
- BCD ADDER USING VERILOG