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IIR
- 用双线性Z变换法设计IIR巴特沃思型数字低通滤波器，能够实现心电信号中随机噪声的去除。-Bilinear Z transform with the design of IIR Butterworth digital low-pass filter, ECG can be achieved in the removal of random noise.
echo1
- Adaptive Echo Canceller Using a Modified LMS Algorithm Abstract –– In this paper, an echo canceller is presented, using an adaptive filter with a modified LMS (Least Mean Square) algorithm, where this modification is achieved coding error on con
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
CPLD_portable_digital_storage_oscilloscope_hardwar
- CPLD的便携式数字存储示波器硬件平台设计-CPLD portable digital storage oscilloscope hardware platform design
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
Digital-image-processing-technology
- 数字图像处理技术,通过系统的学习,可以了解图形软件等的设计原理-Digital image processing technology, through systematic study, to learn graphics software design principles
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
szdyb-proteus-CODE
- 利用proteus软件设计的数字电压表，包含有原理图和程序代码。-Proteus software design using the digital voltmeter, contains schematic and program code.
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
IPTV2
- 当前数字电视中EPG的常用设计方法不适合用来设计IPTV中的EPG。根据IPTV系统的自身特点，本文介绍了一种EPG模块的设计和实现方法。-Current digital TV EPG common design method is not suitable for the design of IPTV in the EPG. IPTV system, according to its own characteristics, this paper presents a EPG module d
Fir
- 窗函数法的Fir数字滤波器设计 Matlab-Window function method of the Fir Digital Filter Design
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
design
- matlab数字信号处理的好算法，可以对处理数字问题达到简便的效果-a good digital signal processing matlab algorithm can deal with the effect of number of issues to simple
Electronic_stopwatch_features_plus_countdown
- 单片机做电子秒表。使用proteus仿真。设计要求：6位LED数码显示，计时单位为1/100秒。利用功能键进行启/停控制。其功能为：上电后计时器清0，当第一次（或奇数次）按下启/停键时开始计数。 当第二次（或偶数次）按下该键时停止计时，在一次按下启/停键时清0后重新开始计时。具有24秒减计数功能。 -SCM in the electronic stopwatch. Use proteus simulation. Design requirements: 6 LED digital dis
digital-lowpass-filter_butter
- 对于给定的滤波器参数，利用脉冲响应不变性法设计数字低通滤波器，并绘出了设计后的数字滤波器的特性曲线。-This code uses impulse invariant method to design a digital low-pass filter under given filter parameters,then it plots the designed filter s characteristic curve.
digital_QAM_receiver
- QAM系统的全数字设计，学位论文，较长较细致，值得参考，不多说，免费下-QAM system, all-digital design, dissertations, longer than the detail, it is also useful, not more than that under free
0608190248xiatao
- 实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。 关键字：数字钟 闹钟 仿真 准点报时 -Quartus II software by means of experimental Lee designed a multi-functional digital clock and real
VLSI
- [電子書籍]利用verilog硬體程式語言來設計大型積體電路的經典書籍 "Digital VLSI Design with Verilog" 由淺入深值得一看 -[E-books] verilog hardware descr iption language used to design large-scale integrated circuit classic books " Digital VLSI Design with Verilog" Deep and worth
IIR(vhdl)
- 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code