搜索资源列表
fir3
- FIR 滤波器 matlab/simulink dsp builder-FIR filter Matlab / Simulink dsp builder
DSP_BUILDER_DESIGN
- DSP Builder设计初步,介绍Matlab/DSP Builder及其设计流程,正弦信号发生器完整的设计过程,以及使用Matlab、quartusII\\modelsim详细的仿真过程。
FIR
- 用DSP BUILDER设计的3阶和四阶滤波器
update_megacores
- 基于matlab和dsp builder的update_megacores详解,主要解决的是update_megacores的问题
DSP1
- DSP子程序,后续会上传DSP builder 基于matlab的相关程序,敬请关注!
Application_in_FPGA_design_of_Matlab_simulink
- 分析了MATLAB/Simulink 中DSP Builder 模块库在FPGA 设计中优点, 然后结合FSK 信号的产生原理,给出了如何利用DSP Builder 模块库建立FSK 信号发生器模 型,以及对FSK 信号发生器模型进行算法级仿真和生成VHDL 语言的方法,并在modelsim 中对FSK 信号发生器进行RTL 级仿真,最后介绍了在FPGA 芯片中实现FSK 信号发生器的设 计方法。
wqdds0727
- 用于的dsp builder的matlab实现算法,产生可编程的sin或cos波形,可以通过它作为ddc的dds
DspBuilder6.0License
- Dsp Builder 6.0 License Dsp Builder 6.0 破解
dds.rar
- 这是用ALTERA里的DSP BUILDER里做的DDS模块,可以在EP1C20400里下载并通过SIGNAL TAP进行在线测试。,It is used inside the DSP BUILDER where ALTERA do DDS module, you can download a EP1C20400 through SIGNAL TAP-line testing.
Crack_Altera_6[1][1].0-9.1
- quartus版本的破解 从6.1至9.0间所有版本-quartus crack version from 6.1 to 9.0 all versions
tes_amp_80_0314
- 基于dsp builder的数字下变频器,IP核做的-digital down converter,degigned in matlab
EP3C8020111219125810_ROM_OK5
- 采用DSP builder v9.1实现正交两路单频输出,已经在EP3C80上面跑通,经实际验证是正确的。此例程非常简洁明了,可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct.
sinout_work
- 自己做的一个最简单的DSP builder列子,对初学者会有一定的帮助,里面还含有程序。-MY sin wave,have cost much time。please use it carefully。
ff
- 在DSP BUILDER上实现数字滤波器-In the realization of digital filters on a DSP BUILDER
dspddc_R12p1
- 基于DSPbuilder搭建的DDC,里面包括CIC滤波器,FIR低通滤波器,HB半带滤波器,NCO等,实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
cic
- 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC,解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Crack_Altera_6.0-9.1
- DSP builder6.0-9.0和quartus ii6.0-9.0等版本的破解器,注意运行破解器时最好关闭杀毒软件,否则有可能会出错-DSP builder6.0-9.0 and quartus ii6.0-9.0 and other versions of the cracker, pay attention to when the best off running the cracker antivirus software, or they may be wrong
DSP
- 基于DSP Builder信号发生器的设计,正弦波,方波,三角波,锯齿波生成-Based on DSP Builder signal generator, sine wave, square wave, triangle wave, sawtooth wave generation
DSP-Crack
- Crack DSP Builder 90.rar cracker
Crack_dsp_builder_11.1
- this file is used to active dsp builder 11