搜索资源列表
tongbu
- FFT实现信号的检测与同步，使用FFT做相关运算，大大缩短了了同步的复杂度和时间，这里是主代码，其他模块QUARTUS中自带有IP核，直接调用就是了-FFT signal detection and synchronization, do the relevant calculations using FFT, greatly reducing the complexity and time synchronization, here is the main code IP core comes
xfft_v8_0_bitacc_cmodel_lin64
- FFT的C模型，用于仿真FFT IP Core的功能-Bit Accurate C Model of Fast Fourier Transform
fft64
- verilog hdl 编写的64点fft代码，适合很多芯片-coded by verilog hdl that implement 64 point fft, suite to many core
1024_FFT_IP
- 实现了1024点FFT的IP核,用起来很方便，直接调用即可-To achieve a 1024-point FFT IP core is easy to use, and can be called directly
Xilinx_FPGA_FFT_Application_Note
- Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！-Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port descr iption and specific settings as well as the source code for digital signa
OFDM
- 正交频分复用(OFDM) 是第四代移动通信的核心技术。该文首先简要介绍了OFDM的发展状况及基本原理, 文章对OFDM 系统调制与解调技术进行了解析，得到了OFDM 符号的一般表达式，给出了OFDM 系统参数设计公式和加窗技术的原理及基于IFFT/FFT 实现的OFDM 系统模型。-Orthogonal frequency division multiplexing (OFDM) is the fourth generation mobile communication core technol
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
fftip_1k
- FFT IP核调用 VHDL语言 quartus -FFT IP core VHDL language called quartus
fft_compare
- matlab file to compare the results of fft function of matlab with fft of xilinx core generator
fft_ly
- 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of
fft256
- 利用FPGA ip核实现256点的FFT转换，用vhdL语言实现。-Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.
fft_test
- ALTERA的FFT IP核时序的仿真，verilog语言。采用burst方式，FFT点数2048点-FFT IP core of timing simulation ALTERA, verilog language. Using burst mode, FFT points 2048 points
fft512_ipcore
- 512点的FFT 使用IP核 帮助新手理解-Using a 512-point FFT IP core to help the novice to understand
top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
MyFFT
- 该程序可实现基于IP核的FFT算法，TESTBENCH用TEXTIO输入输出数据-The program can achieve FFT algorithm based on IP core, TESTBENCH based on TEXTIO input and output data
vlfft
- 基于8核DSP的超大数据量FFT的分解算法和并行实现源码，语言为嵌入式C，内部有配置说明。-Based on 8 core DSP of the large data volume of FFT decomposition algorithm and parallel implementation source code, language for embedded C, the internal configuration.
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
adsp-2191_complex_rad2_fft
- ADSP-219x Complex Rad2 FFT.zip中的文件可部署长度为64或更长的单核radix-2 FFT-This directory contains an example ADSP-2191 single-core subroutine that implements radix-2 FFT of length 64 or greater on input data x(n). A detailed discussion of the complex radix-2
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content