搜索资源列表
fpadd
- 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
dspzs
- 本书全面系统地介绍了DSP芯片的基本原理、开发和应用。首先，介绍了目前广泛使用的DSP 芯片的基本结构和特征，定点和浮点DSP处理中的一些关键问题。然后，对用C 语言和MATLAB 语言进行DSP算法的模拟进行了介绍。-This book a comprehensive and systematic introduction to the basic principles of DSP chips, the development and application. First of all, o
ALU-FP
- ALU floating point 8 bit
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
DualDSPbasedembeddedvisualfeedbackcontrolsystemfor
- 为了满足多种电力电子变换器对其控制平台的不同要求,缩短开发时间,实现控制平台硬件的通用化和软件 的模块化,在基于双定点数字信号处理器(DSP)TMS320LF2407的大容量变换器专用控制平台的基础上, 提出了电力电子变换通用控制平台的设计目标。描述了基于定点和浮点DSP(TMS320F2812和TMS320VC33)的通用 控制平台各单元的设计方法。介绍了基于MATLAB实时工具箱(RTW)的调试方法。实验结果验证了设计和调试方法 的正确性和可行性,该通用控制平台达到了设计目标
IEEE_754_Floating_Point_Conversion_from_32_bit_He
- conversion From 32-bit Hexadecimal Representation To Decimal Floating-Point Along with the Equivalent 64-bit Hexadecimal and Binary Patterns
在VHDL中实现高精度快速除法
- 高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point
floating_point_adder
- 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
undistort
- floating point arthematic function with verilog code
Floating-point
- 浮点数转化为字符数组，方便单片机数据存储和处理。-Floating-point numbers into an array of characters to facilitate data storage
Floating_Point
- 简单的浮点的内核测试，已经验证通过，VLOGER编写-The core of a simple floating-point test has been adopted to verify, VLOGER prepared
fpadd
- Floating point adder
69491706fp_add_sub
- verilog code for floating point adding
divider_latest.tar
- floating point divider
tricordic
- 用CORDIC计算器计算sin,cos。包含浮点仿真模型和定点仿真模型-CORDIC calculator with sin, cos. Contains the floating-point simulation model and the fixed-point simulation model
fixed_point
- - for floating point to fixed point - seperate to integer and fraction part
floating_multi
- Floating point multiplier
mult
- floating point multiplier
RVDS
- ARM公司RVDS开发工具的中文说明书，内容十分详尽！ 包括安RVDS安装指南.pdf、RVCT要点指南.pdf、RVCT开发指南.pdf、RVCT汇编器指南.pdf、RVCT编译器用户指南.pdf、RVCT链接器用户指南.pdf、RVDS入门指南.pdf、ARM® Workbench IDE 用户指南.pdf、RVCT编译器参考指南.pdf、RVCT库和浮点支持指南.pdf、RVCT链接器参考指南.pdf、RVCT实用程序指南.pdf-ARM' s development to