搜索资源列表
RS-encode_FPGA
- 利用FPGA开发软件 进行rs编码的仿真 模拟RS编码的过程步骤-rs code in FPGA
music
- FPGA完成《友谊天长地久》的编码,并已通过实测-FPGA to complete the "friendship forever"
Modulater-and-Encoder
- 无线光通信中基于FPGA的高效编码调制器设计,很有参考价值.-Design of High Efficiency Modulater and Encoder Based on FPGA in FSO Communication System.
16Kbs_MELP
- 16Kbs类MELP语音压缩编码器的FPGA实现-16Kbs MELP speech compression encoder FPGA implementation
ps2
- fpga ps2接口控制 能够实现ps2键盘扫描 在数码管上显示出相应编码-fpga ps2 interface
OFDM_FPGA
- 采用FPGA 来实现一个基于OFDM 技术 的通信系统中的基带数据处理部分,即调制解调器。其中发射部分的调制 器包括:信道编码(Reed-Solomon 编码),交织,星座映射,FFT 和插 入循环前缀等模块。-FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modul
8b10_enc
- 8B10B是应用最广泛的编码技术。它被用于串行连 接SCSI、串行ATA、光纤链路、吉比特以太网、XAUI(10吉比特接口)、PCIExpress总线、InfiniBand、 SeriaRapidIO、HyperTransport总线以及IEEE1394b接口(火线)技术中。-8b/10b has been widely adopted by a variety of high speed data communication standards used today and should
diffdecoding
- 基于FPGA的差分编码,环境为QuartusII,语言为Verilog-Differential coding differential encoding differential encoding differential encoding differential encoding
I50550PWM_V55m
- FPGA 实现一种基于ISA接口的3路编码器计数,与3路PWM/DDA输出编码器计数包含倍频、鉴相PWM实现12位分辨率 已通过测试。 -FPGA implementation based on the ISA interface, 3 channel encoder count, and 3-way PWM/the DDA output encoder count contains a multiplier, the phase PWM 12-bit resolution has been
CODER
- 基于FPGA的8线-3线优先编码器的设计,QuartusII编译通过,采用VHDL语言编写。-Based on FPGA eight line-3 line is preferred encoder design, QuartusII compile, USES the VHDL language.
mkjpeg.tar
- 用FPGA实现的JPEG编码器,可以直接使用,内含完成说明文档,经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
RS_Encoder
- 具有16个校验位的RS编码器,在FPGA上实现。-With 16 RS encoder, the parity bit in the FPGA.
20120715081838335
- ise13.1使用说明,如何编码,综合,仿真,并烧录到FPGA板验证-ise13.1 instructions for use, how to encode, synthesis, simulation, and burn to the FPGA board verification
Example-8-1
- 我的观点是Verilog和VHDL对于高手而言各有利弊,Verilog感觉更适合于RTL(寄存器传输级)的描述,而VHDL更适于System级的建模。 但是初学者强烈建议学习Verilog,更容易入手些,但是学习过程中一定要注意下面一点,毕竟国内外大公司现在大都采用Verilog是有其原因的。 l FPGA/CPLD、ASIC的逻辑设计所采用的硬件描述(HDL)语言是同软件语言(如C,C++等)是有本质区别的!虽然Verilog很多语法规则和C语言相似,但是Verilog是硬件描述
HDB
- FPGA实现HDB3码的编码与译码 采用EDA工具中的Quartus II 8.1作为软件平台,实现HDB3码数字基带信号的编码和译码。-FPGA Implementation of the HDB3 code encoding and decoding using Quartus II 8.1 EDA tools as a software platform, achieve the encoding and decoding of the HDB3 code digital baseba
Core_fifo_w
- FPGA写FIFO操作,然后把FIFO里的数据送到编码器里编码成PAL格式,输出-write a picture to the fifo odd and evea ,then it can be used to encode into the PAL to display
crc16_8bit.v
- FPGA用于实现crc16编码的verlog源程序,用到的请下载。-FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.
coding
- FPGA在通信上的运用:基于FPGA的VHDL的HDB3编码-FPGA communications: HDB3 encoding FPGA VHDL-based
huffman(z)
- HUFFMAN编码,压缩,解压缩,FPGA课设用的-huffman code and encode
manchester
- 使用VHDL语言编程,在FPGA上实现曼彻斯特编码,可用于通信领域编码。-VHDL language programming, implemented on FPGA Manchester encoding can be used in the communication field coding.