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4yue11haoxiawu
- 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the soft
Automatic_generation_of_neural_networks_for_image_
- 提出了利用FPGA的现场可编程以及可并行处理的特性，对基于人工神经网络的图像处理结构进行自动生成的一种技术。作者：Andre B. Soares, Altamiro A. Susin，Leticia V. Guimaraes
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
gps_tracking
- 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulati
Fingerprint_Normalized_FPGA_code
- 指纹图像归一化FPGA代码,v格式，不错的代码-Fingerprint image normalization FPGA code, v format, a good code
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
f32c-master
- FPGArduino源码，f32c：VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
float_2_int.v
- 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
Norflash_readid
- 通过镁光官网下载Norflash模型，然后编写v文件进行读取id测试，最后下载到FPGA板子，可以验证FPGA外接的Norflash是否工作
freedom-master
- This is a feedom master version of the RISC-V core and can be used with LGPL license
8-tile-puzzle-master
- BVNGBFGJHN SDOIV KJCXVN DVK DVOI V DVNKL LV
liushuideng
- Cyclone V开发实验板实现FPGA的8位流水灯(Cyclone V development of experimental board to realize 8 bit flow lamp of FPGA)
FPGAstudy
- CYCLONE V实现按键对LED灯的控制(CYCLONE V control the control of LED lamp)
miaobiao
- Cyclone V开发板实现数字秒表功能，带有启动，暂停，复位功能。可以显示小时，分钟，秒。(Cyclone V development board implements digital stopwatch function, with start, pause, reset function. It can be shown hours, minutes, seconds.)
C5GX开发板原理图和PCB
- Altera_Cyclone V GX FPGA Development Kit原理图PCB 供参考(Altera_Cyclone V GX FPGA Development Kit_sch_pcb)
9268
- 国产9268 配置FPGA 码 ，AD9268是一款双通道、16位、125 MSPS模数转换器(ADC)，设计用来支持需要高性能、低成本、小尺寸且具多功能性的通信应用。(adi ad9268 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter)
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)