搜索资源列表
DSP_DesignFlow_User_Guide
- DSP Builder开发全部流程介绍,从事FPGA开发与设计的人员使用-DSP Builder development of all the processes introduced in FPGA development and design staff to use
fira
- 这是一个用FPGA中DSP Bulider做的一个FIR滤波器，很好使用，我已经测试过了-This is an FPGA, DSP Bulider used to do a FIR filter, a very good use, I have tested the
dspddc_R12p1
- 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Sp3A-DSP-1800A-Starter-Schematic-Rev1
- spartan1800A的原理图和资料，有了它的，我们的设计就会快捷方便许多了-Spartan-3A DSP FPGA Board and Kit Documentation.
matlab_dsp_building
- matlab dsp building fpga-matlab dsp building
BPSK_track_10.23M_BD_IF46.52MHz
- in tracking programm，actualize communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result-communications between DSP and FPGA Besides produce ahead code present code late code and correlation
High-speed_signal_processing_FPGA-DSP_design
- 我上传的是一个高速信号处理FPGA-DSP设计-High-speed signal processing FPGA-DSP design
FTOD_SDRAM10.3.18
- FPGA与DSP数据接口转换时序，简单实用的，SDRAM时序读写数据。-FPGA and DSP data interface conversion timing, simple and practical, SDRAM read and write data timing.
Three_axis_tumtable_control_system_design_based_on
- 硕士论文 一阐述了本论文的研究背景和意义，综合评述了国内外三轴转 台的发展现状，提出了论文的主要研究内容。 二通过对转台总体指标进行分析，确定以FPGA+DSP为系统的硬 件平台，以直流力矩电机为控制对象，以感应同步器为测角传感器的 整体方案设计。 三针对转台的特性参数，进行了直流力矩电机，以及整个系统 的建模，并采用全数字PID算法进行系统仿真，对仿真结果进行了分 析。 四针对转台在运行过程中负载力矩的不确定性，提出采用模糊 控制的方法对转台进行控制，详细阐
dsp
- dsp2812板子的所有资料，包括pcb板子和sch板子！-dsp2812 board of all information, including sch pcb board and the board!
5546546516
- ARM,DSP,FPGA 的解释与说明A RM,DSP,FPGA 的解释与说明-ARM,DSP,FPGA ARM,DSP,FPGA ARM,DSP,FPGA
sopc
- 文件包括：FPGA及DSP+Builder Nios II Software User guide chinese NIOSII那些事 Nosi Ⅱ入门 SOPC系统设计入门教程-Documents include: FPGA and DSP+ Builder Nios II Software User guide chinese NIOSII those things Nosi Ⅱ entry SOPC Design Tutorial
IP
- this a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .-this is a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can dow
OFDM_Security
- This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simul
FPGA-and-DSP-based-on-the-Bayer-format-image-pre-p
- 在图像实时处理的过程中，下层图像预处理的数据量大，运算简单，但是要求运算速率高，可以用FPGA硬件来处理，上层所处理的数据量少，算法结构复杂，适于运算速度快，寻址灵活的DSP数字信号处理器进行处理。该系统充分发挥了FPGA和DSP各自的优势，能更好地提高图像处理的实时性，降低成本。 -Real-time processing in the image process, the lower the amount of data preprocessing, simple operation,
lab_instructions1
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions2
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions3
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
Spartan-3ADSPs
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
SJA1000
- SJA1000驱动程序。它是CAN BUS通讯的控制器集成电路。可与DSP,FPGA连接-SJA1000 driver. It is the CAN BUS communication controller IC. With DSP, FPGA connections