搜索资源列表
sdram_ver_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
PIC10_RISC_Verilog
- The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming
8086IP
- 用硬件描述语言编写的8086 IP CORE-Using hardware descr iption language of the 8086 IP CORE
IPcore
- 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
C8051_mega_core.tar
- 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
altera_up_avalon_sd_card_interface_91
- 修改后的Altera大学计划IP Core，可用于QII9.1及9.1SP1-Revised Altera University Program IP Core, can be used for QII9.1 and 9.1SP1
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
CANProtocolControllerIPCoreinVerilog
- 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
usb20_ipcore_usb_funct
- usb 2.0协议的ip核，可用，里面程序有文档说明-usb 2.0 protocol ip core, can be used, which procedures are documented
8051IP
- mc8051 IP Core源代码供学习和研究，严禁用于商业目的-mc8051 IP Core source code available for study and research for commercial purposes is strictly prohibited
sd_slave_device
- verilog source code for SD card SLAVE DEVICE IP-Core
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
TERASIC_AUDIO
- 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
image_control
- NIOSII通过IP核读取CMOS图像传感器在SDRAM中的数据-NIOSII read through the IP core in CMOS image sensor data in SDRAM
vga_ip_v1_00_a
- This simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.-This is simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.