搜索资源列表
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
MC8051 IP Core
- 8051的IP软核，使用硬件描述语言编写，可以下载到FPGA/CPLD中作为片上系统的处理器-8051 IP soft-core, the use of hardware descr iption language can be downloaded to the FPGA / CPLD as a system-on-chip processor
fpga 8051单片机IP核
- fpga 8051单片机IP核。This is version 1.3 of the MC8051 IP core-8051 IP core. This is version 1.3 of the IP core MC8051
FFT变换的IP核的源代码 VHDL~
- FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
opb_vga.EDK下的用户IP核
- 一个EDK下的用户IP核，进行OPB总线到VGA的转换,EDK under a user IP core, the OPB bus to VGA conversion
sha1_v01.zip
- SHA-1加密算法的IP核，内涵文档，仿真测试文件,SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
C8051IP.rar
- FPGA应用，51单片机的IP核，在FPGA中嵌入单片机的源代码,FPGA applications, 51 MCU IP core, single-chip embedded in the FPGA source code
mc8051_design
- 使用VHDL语言，实现C8051 IP Core(Use VHDL, Realize C8051 IP Core)
SPWM信号产生系统IP软核设计及验证
- 针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full
不用IP核设计乘法器
- VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)
XPS_Custom_IP_Tutorial_2
- Custom IP Core Development tutorial in Xilinx XPS
XPS_Custom_IP_Tutorial_3
- Custom IP Core Development tutorial in Xilinx XPS Part 3
XPS_Custom_IP_Tutorial_1
- Custom IP Core Development tutorial in Xilinx XPS Part 1
XPS_Custom_IP_Tutorial_4
- Custom IP Core Development tutorial in Xilinx XPS Part 4
ft2232hcore_latest.tar
- ft2232 IP Core
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
IP核的生成
- 讲述了FPGA中IP核的使用方法，对于初学者很有帮助。(The method of using IP core in FPGA is described.)
基于IP核的ISE设计流程
- 讲述了在ISE中如何通过建立ip核，使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
hdl-master
- adi devices ip core, inc. ad9361/xxx