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ADC_TIM2
- ADC定时器控制采样，单路，可根据此代码扩展多路-ADC sampling timer control, single, according to this code multiplexer expansion
11
- 基础实验_01_多路复用器 ：4通道8位带三态输出-Experimental basis _01_ multiplexer: 4-channel 8 with a three-state output
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
BusMultiplexer
- 基于DSP48E1的BUS MULTIPLEXER-Based on the BUS MULTIPLEXER DSP48E1
magnitude-comparator-and-mux
- Magnitude comparator and multiplexer codes in Verilog
mux_3_conditional
- implementation of multiplexer using conditional operator
mux3_case
- implementation of multiplexer using case statements in verilog
mux3_if_else
- implementation of multiplexer using if else statement in verilog
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
ps2mult
- TQC PS 2 Multiplexer driver for Linux.
muxp
- a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the
clk-mux
- Simple multiplexer clock implementation for Linux Device.
pio
- Atmel PIO2 Port Multiplexer support for Linux.
Tim
- STM32F103 高级定时器1输出多路PWM，还可以设置死去时间，讲解详细-STM32F103 Advanced Timer 1 output multiplexer PWM, you can also set the dead time to explain in detail
GSM
- 基于51单片机，通过GSM模块短信遥控多路开关.购买的是联通的不记名卡，实测有效，但短信接受偶尔有10秒以内的延迟.-Based on 51 single-chip, via GSM SMS remote multiplexer module. Purchased Unicom anonymous card, the measured effective, but occasionally there is a delay accepting messages within 10 seconds
1.1Generic-Mux-VHDL
- generic 2to1多路复用器,用behavior和structure两种方式写的!-generic 2to1 multiplexer with behavior and structure are two ways to write!
fuyong
- 四路四bit时分复用复接器设计，完成拨码开关式输入的复接器。-Four-four time division multiplexing bit multiplexer designed to complete the DIP switch inputs of the multiplexer.
mux
- 使用VERILOG實現多工器之設計,並附上tb供測試-VERILOG realized using multiplexer design, along with tb for testing
FPGA1
- 基于FPGA的多路复用器，4通道8位带三态类型-Multiplexer, 4 channel 8 bits with three states type
multi-plexer
- in this project i use a multiplexer for show munmber on it