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PhaseLockedLoop
- phase lock loop for coherent detection
gfuzzy
- 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
LMX2347
- VHDL code for LMX2347(Phase lock loop)
FAQLPC2xxxPLLFamilyPhaseLockLoop
- This application note describes the different blocks of the Phase Lock Loop in the LPC2000 family of Philips ARM7 Microprocessors.
synchronization
- 采用AFC技术来锁定频，采用Garden技术进行定时恢复，采用Costas环进行相位的锁定-Use technology to lock the frequency of AFC, using Garden timing recovery techniques using Costas loop for phase locking
pll_manual
- This book is document about "Phase lock loop"
LoopFilterMatrix
- phase lock loop pll toolbox tool
cppll
- Simulink analog phase lock loop
powerpll
- Simulink power phase lock loop
PLL_ars
- phase lock loop method
Frequency-Synthesis-by-Phase-Lock
- 老外的一本绝版好书，绝版~有钱买不到的东西-Foreigners an out of print books, out of print ~ the things money can not buy
DPLL
- 模数转换的数字锁相环，代码中有详细的说明-digital phase lock loop
PLL
- Performance of Phase Lock Loop in fading channel
sim_PLL
- This shows how the phase lock loop can be designed and system parameter dendancy verified through simulation
PLL
- 在同步控制上，应用了“优先与抢占”的方式产生同步信号，纯硬件实现，简单可靠；使用了成熟的数字锁相环来跟踪同步信号。-A strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase-lock loop to track synchronization signal
3.2_SetPLL
- 流明ARM开发板设置PLL锁相环时钟示例程序，可以直接在IAR编译器上运行使用。-Lumens ARM development board PLL set phase lock loop clock example program, can direct IAR compilers run use.
weitb
- 在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving direc
pll
- phase lock loop amjadmftah@hotmail.com
phase-lock-loop
- 编制Matlab仿真程 序。通过计算机仿真比较可以得出动态（捕获）性能，并画出改变某个参数条件下的响 应曲线，根据仿真结果更加直观、系统地分析环路的动态性能，为采样锁相环的研究和 工程设计提供参考。 -Through the computer simulation comparison can be obtained dynamic (capture) performance, and draw a change under a certain parameter condit