搜索资源列表
EDA1
- 掌握Quartus II 的VHDL 文本设计的全过程; (2)熟练和掌握EDA设计流程;熟悉简单组合电路的设计,掌握系统仿真,学会分析硬件测试结果。 (3)学习PH-1V型实验装置上发光二极管和按键的使用方法。 -Quartus II VHDL text grasp of the whole process of design (2) skilled and master the EDA design flow familiar with the simple combinat
EDAmusicplayer
- EDA乐曲播放器,在EDA开发工具Quartus II 6.0平台上,采用VHDL语言层次化和模块化的设计方法,通过音符编码的设计思想,预先定制乐曲,实现动态显示乐曲演奏电路的设计-EDA music player
MIMASUO
- 伴随着集成电路(IC)技术的发展,EDA技术已经成为现代电子设计的发展趋势,并在各大公司、企事业单位和科研教学部门广泛使用。VHDL是一种全方位的硬件描述语言,几乎覆盖了以往各种硬件描述语言的功能,整个自顶向下或自底向上的电路设计过程都可以用VHDL来完成。本文阐述了EDA的概念和发展、VHDL语言的优点和语法结构并分析讲解了智能抢答器的各模块的功能要求、基本原理以及实现方法。本系统的设计就是采用VHDL硬件描述语言编程,基于Quartus II平台进行编译和仿真来实现的,其采用的模块化、逐步细
FSK
- FSK调制与解调,用VHDL语言实现,在QUARTUS软件运行-FSK
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
tutorial_quartus
- this is a quartus tutorial
sys_cpt
- 10.0 quartus 的破解文件,把这个文件替换就可以了 -10.0 quartus the crack file to replace the file on it
CPU
- 一个完整的流水CPU设计,quartus平台,Verilog实现-CPU design a complete water, quartus platform, Verilog realization
crc16_finished
- 使用Quartus II软件开发,编程语言为Verilog,实现的是FPGA源代码-Using the Quartus II software development, programming languages Verilog, FPGA source code to achieve the
DSP_Builder_user
- dsp_builder使用方法 教你如何利用matlab和quartus交互使用定制dsp-dsp_builder teach you how to use matlab and dsp quartus interactive use of customized
Quartus_II
- 中文版的quartus官方教程 很方便学习
S1_12864lcd
- FPGA实用程序,测试lcd12864,开发环境为Quartus II 8.0 (32-Bit),已经测试ok,供大家参考学习-FPGA utility, test lcd12864, development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
S8_SETPMOTO
- FPGA实用程序,测试步进电机,开发环境为Quartus II 8.0 (32-Bit),已经测试ok,供大家参考学习-FPGA utility, the test motor, development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
S5_KEY2LED
- FPGA实用程序,测试key与led,开发环境为Quartus II 8.0 (32-Bit),已经测试ok,供大家参考学习-FPGA utility, test key and the led, the development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
baseband_code
- 利用VHDL硬件语言编写了常用的基带码的产生,Quartus ii 仿真通过。-Written by VHDL hardware language code commonly used in the generation of baseband, Quartus ii simulation pass.
Binary.code.Gray.code.converter
- 二进制码格雷码转换器 进行二进制码格雷码转换,vhdl,QuartusⅡ-Binary code Gray code converter
Counter
- 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端,CLR为清零端,Y[3..0]为四位二进制输出(BCD 码形式),CLKOUT为10进制计数器进位输出端 -Counter
clock
- 多功能数字钟,、在Quartus 2环境中编译通过; 4、仿真通过并得到正确的波形; 5、给出相应的设计报告 -clock
AMI_HDB3
- VHDL实现AMI码和HDB3码之间的相互转换,编译环境为Quartus II 6.1-HDB3 AMI code and VHDL code to achieve conversion between, the build environment for the Quartus II 6.1