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src
- 在spartan3e实验板上实现交通灯的功能，采用状态机描述。-traffic lights design on spartan3e board
spartan3e
- this source is pin ucf for spartan 3e
spartan_3e_DAC
- 自己写的一个可以在spartan3e板子上实现使DAC输出电压为2V的一个程序。-The written a spartan3e board DAC output voltage of 2V a program.
spartan3e_ps2
- verilog语言编写在spartan3e板子上实现，利用板子上的8个LED灯显示键盘输入的编码值。-the Verilog language spartan3e board, 8 LED lights on the board display keyboard input encoded value.
spartan_3e_uart_tx
- 使用verilog语言编写的串口发送程序，波特率9600，spartan3e板子验证。-Serial Send procedure using Verilog language, baud rate 9600, spartan3e board to verify.
spartan_3e_uart_rx
- 使用verilog语言编写的串口接送程序，波特率9600，spartan3e板子验证。-Serial Shuttle program using verilog language, baud rate 9600, spartan3e board to verify.
Lab_COUNTER
- Lab experiment : 50 MHz clk 4 bit counter (CLR + parallel load + pause ) on spartan3e
FPGA-select
- Spartan3芯片的选择,包括Spartan3 ，Spartan3a，Spartan3e-who to select the chip of Spartan3
TAXI_TOLL_1_1
- 实现出租车自动计费器 能进行LCD1602液晶显示。硬件平台：Xilinx Spartan3E -Use VHDL languange to achieve the automatic taxi meter and display cost,waiting time and distance on the LCD1602 . Hardware platforms: Xilinx Spartan3E
Keyb27Seg
- VHDL codes for Multiplexed 7 segment LED, verified for Spartan3E (Basys2) FPGA board. This is part of Digital System Design course at Fasilkom UI.
led
- ISE开发软件、spartan3e开发板，左右两个按键控制8个发光二极管的左右移动点亮-Eight light-emitting diode the ISE development software, spartan3e, development board, around two button control and move around lit
lcd
- verilog语言，该程序用于描述spartan3E开发板上的lcd的显示，对于其他的lcd显示可以从此程序修改并直接运用-verilog language, the program for describe spartan3E development board lcd display for other lcd display, can begin to changes in procedures and the use of direct
led3
- lcd interface in spartan3e code with verilog domine
sp3e_fifo
- xilinx spartan3e fifo读写测试工程 仿真通过。全套工程。-xilinx spartan3e fifo read and write test engineering simulation through.
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
VHDL_uart
- 用xilinx的FPGA-spartan3E实现uart，固定波特率9600，偶校验，系统时钟50MHz，能够实现将从串口调试助手发送到FPGA的数据重新发回串口调试助手-using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant
Xilinx_Spartan3E_VGA_PS2
- 使用Spartan3E 开发板实现VGA显示和PS2键盘接口，完成了简单的文字处理功能和图片显示功能。-Use Spartan3E development board to achieve VGA display and PS2 keyboard interface, complete a simple word processing features and picture display.
UniversalDIV
- UNIVERSAL FREQUENCY DIVIDER pin sets for Digilent Basys 2 (Spartan3E-250) fout = (K(0)*100+ K(1)*10 + K(2))*10K(3)
prog_seq_FIN
- Verilog Programmable Sequence Detector on Spartan3E
Counter_Debounce
- Verilog 3-bit Inc/Dec Counter on Spartan3E